GSoC 2026 - BlackParrot UVM Testbenches Applicant

[Aman Sharma]

Hi everyone,

I'm Aman Sharma, B.Tech ECE student applying for the BlackParrot
UVM testbenches project.

Background:
- Built FPGA verification infrastructure (self-checking testbenches)
- Project Helios: Packet monitoring engine with comprehensive verification
- Currently learning UVM methodology for processor verification

Work completed so far:
- Forked BlackParrot and analyzed codebase
- Selected 3 modules following Dan's progressive difficulty strategy:
  1. bp_be_int_box.sv (38 lines - combinational)
  2. bp_be_top.sv (254 lines - integration)  
  3. bp_be_csr.sv (702 lines - complex stateful)

- Deep dive analysis of Module 1 (bp_be_int_box)
- Designed verification strategy (50 directed + 10K random tests)
- Created 12-week implementation timeline
- Learned UVM basics (Verification Academy + UVM Cookbook)

Repository: github.com/Captain1508/black-parrot
Analysis: See module1_deep_dive.md and verification_plan.md in fork

Questions for Dan (when you have time):

1.Module 1 verification scope: Should I focus purely on unit-level
   verification of bp_be_int_box, or also verify its interaction with
   surrounding calculator pipeline modules?

2.Coverage expectations:Target 100% functional + code coverage, or
   is there a different threshold you'd recommend for BlackParrot?

3.Verilator integration:Any known limitations with Verilator's UVM
   support that I should plan around? Should I have a backup simulator
   (VCS/Questa) ready?

4.BlackParrot-specific corner cases:Are there RISC-V ISA extension
   behaviors or BlackParrot implementation quirks I should test
   specifically for the integer boxing module?

Looking forward to feedback and contributing to BlackParrot verification!

Best,
Aman Sharma

Links:
- BlackParrot fork: github.com/Captain1508/black-parrot