Emulation of black-parrot on FPGA

[Yasas Senevirathne]

Hi,

I appreciate the team for open-sourcing and supporting blackparrot development.

I'm trying to run several experiments on a blackparrot core emulated on an FPGA. The planned experiment is to load a blackparrot core onto an FPGA, boot Linux on the core (I would also like to try bare metal), and run an experiment program.

Going through the documentation I realized that I could emulate black parrot using 

1. Litex
2. ParrotPiton
3. Zynq-parrot

I focused on trying out Zynq-parrot because it was the most up-to-date. 

From what I understand Zynq-parrot is better suited for co-simulation. Going through the scripts I realized that it requires a PYNQ-Z2 development board and did not have a supported shell to access the Linux running on the emulated core (Correct me if I have misunderstood).

Could you please let me know or point me to a resource on how I can do the above-mentioned experiment on a Xilinx FPGA that does not have a Zynq SoC?

Thank you,

Yasas

[Dan Petrisko]

Hi Yasas,

ZynqParrot is of the three best supported at the moment and does support co-simulation.  It will work most easily with any Zynq FPGA (not just Z2). 

For non-Zynq FPGAs, ZynqParrot supports a UART emulation bridge. This does require a UART connection to your board.  There is a standalone example here: https://github.com/black-parrot-hdk/zynq-parrot/blob/master/cosim/uart-bridge-example/bridge/Makefile. 

There is not currently an example of integrating BlackParrot with this UART bridge; however, it should be possible with a little effort. The only file that you would need to write would be the IP block creation script. In this, you would hook up the UART bridge between your external UART and the AXIL interfaces of the Zynq Shell 

- https://github.com/black-parrot-hdk/zynq-parrot/blob/master/cosim/uart-bridge-example/vivado/vivado-create-block.bridge.vu47p.2019.1.tcl

  - (in our example, we use a vu47p board with a hacked up UART, refer to your board's .xdc to figure out how to interface)

- https://github.com/black-parrot-hdk/zynq-parrot/blob/master/cosim/black-parrot-example/vivado/vivado-create-block.zynq.ultra96v2.2020.1.tcl

Note that the UART shell is a) a prototype and b) pretty slow. It's mostly for program loading + configuration when other options are not available.

I'm not sure what you mean about accessing Linux running on the emulated core. Can you clarify?

Best,

Dan

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[Yasas Senevirathne]

Hi Dan,

Thank you for the very quick response. I have access to an Ultrazed-eg SoM which has a Zynq SoC. From what I understand from the scripts in ZynqParrot, you seem to use a python api to load the bitstream to the PL(let me know if I have misunderstood). In Ultrazed-eg the flow requires petalinux to be built from scratch together with the design going into PL. 

Is there a workaround for this? Or am I missing something?

Thank you again,

Yasas

[Dan Petrisko]

Hi Yasas,

I see, got it. That's much easier to work around.  We use Pynq for convenience, but once the PL bitstream is created you can flash it yourself using whatever flow. And then just omit the bitstream-related instructions when running on the Zynq

Best,

-Dan

[Yasas Senevirathne]

Hi Dan,

Thank you for the suggested workaround. Unfortunately, I ran into issues setting up the petalinux flow to work with the zynq-parrot example. I was able to find a PYNQ-Z1 development board that has the same chip as the PYNQ-Z2 board.  I was able to generate the packed bitstream following the instructions in https://github.com/black-parrot-hdk/zynq-parrot/tree/master/cosim/black-parrot-example. I was also able to build the toolchain following the instructions in https://github.com/black-parrot-hdk/zynq-parrot/tree/master. 

I was also able to copy the packed bitstream onto the PYNQZ1 development board and load it using the provided makefiles. I am now trying to run an example on the board. I realized that I needed a generated nbf file for this. Could you please tell me how or point me to a resource that has the required steps to generate a nbf file from a source c file?  

I also found that black-parrot-sdk has several benchmarks and tests (https://github.com/black-parrot/black-parrot/blob/master/docs/testbench_guide.md ). It would be great if you could provide me with more information on running these on the FPGA.

Thank you,

Yasas

[Daniel Petrisko]

Hi Yasas,

If you’ve built the SDK, then “make hello_world.nbf” in black-parrot-example/verilator should work. 

That target searches the installed programs in black-parrot-sdk/prog. So if you have a custom .riscv, you can copy it in that directory first, then generate the nbf. 

Best,

-Dan

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[Yasas Senevirathne]

Hi Dan,

I was able to run the balck-parrot-example on the PYNQ-Z1. Thank you for the help!

Yasas

[Daniel Petrisko]

Great! Glad to hear it. 

Best,

-Dan

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[Yasas Senevirathne]

Hey Dan,

After the black-parrot-example emulation, I wanted to simulate a multicore design on FPGA for my experiment. I was able to get the configuration I wanted to synthesize on Vivado (e_bp_multicore_2_cfg). However, the development boards I have access to (PYNQ-Z1 and KV260) do not have the resources to place and route the design. Could you please tell me what development board you are using to emulate these larger designs?

Thank you,

Yasas

[Daniel Petrisko]

Hi Yasas,

We use vu37p/vu47p. Other collaborators have used enclustra SoMs. Generally ultrascale+ parts tend to be big enough. 

Alternatively, you can try shrinking the caches/predictors/etc by playing with the configuration in black-parrot-example/v/bp_common_pkg.sv, though there is a limit on how small it can get

Best,

-Dan

On Feb 17, 2024, at 4:07 PM, Yasas Senevirathne <nayomalse...@gmail.com> wrote:



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