Stream Hammer, Stream accelerator loopback and other applications

[Ruchita]

Hi Dan,

I was simulating in VCS for hammerblade-example for these applications:

stream_hammer, streaming_accelerator_loopback,streaming_accelerator_vdp, coherent_accelerator_vdp

I am getting following error in simulation:

INFO:    ps.cpp: Starting BP i/o polling thread

zynq-parrot/import/black-parrot-subsystems/manycore/v/bsg_manycore_endpoint_to_fifos.sv", 313: bsg_nonsynth_zynq_testbench.dut.top_fpga_inst.mc_ep_to_fifos.unnamed$$_0: started at 21533650000ps failed at 21533650000ps
Offending 'mc_req_we_lo'
Error: "zynq-parrot/import/black-parrot-subsystems/manycore/v/bsg_manycore_endpoint_to_fifos.sv", 313: bsg_nonsynth_zynq_testbench.dut.top_fpga_inst.mc_ep_to_fifos.unnamed$$_0: at time 21533650000 ps
[BSG_ERROR] Host interface cannot respond to read requests
"zynq-parrot/import/black-parrot-subsystems/manycore/v/bsg_manycore_endpoint_to_fifos.sv", 313: bsg_nonsynth_zynq_testbench.dut.top_fpga_inst.mc_ep_to_fifos.unnamed$$_0: started at 21540550000ps failed at 21540550000ps
Offending 'mc_req_we_lo'
Error: "zynq-parrot/import/black-parrot-subsystems/manycore/v/bsg_manycore_endpoint_to_fifos.sv", 313: bsg_nonsynth_zynq_testbench.dut.top_fpga_inst.mc_ep_to_fifos.unnamed$$_0: at time 21540550000 ps
[BSG_ERROR] Host interface cannot respond to read requests

What does it mean? Has it tested on Hammerblade/BP in VCS?

Regards,

-Ruchita

[Dan Petrisko]

As the names suggest, those tests are written for a BlackParrot multicore processor with attached accelerators, which is a very different system than you are simulating

There is a (very old) accelerator developer guide in the black-parrot repo docs/ that describes the tests and integration strategy 

Best,

-Dan

On Mar 10, 2026, at 7:46 PM, Ruchita <sonal.nil...@gmail.com> wrote:

Hi Dan,

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[Ruchita]

Hi Dan,

I was going the file: https://github.com/black-parrot-hdk/zynq-parrot/blob/master/cosim/hammerblade-example/v/bp_common_pkg.sv  in line 92 and line 104 you mentioned custom BP configuration generated from Makefile and `defines, can you guide which Makefile and  'defines  and how to generate custom BP configuration ?

Regards,

-Ruchita

On Wednesday, March 11, 2026 at 12:19:06 PM UTC+5:30 Ruchita wrote:

Yes, I found the link you are referring to : https://github.com/black-parrot/black-parrot/blob/master/docs/accelerator_guide.md but if I want to simulate to hammerblade then changing to config to ,e_bp_multicore_hammerblade_cfg=4, at https://github.com/black-parrot-hdk/zynq-parrot/blob/master/cosim/hammerblade-example/v/bp_common_pkg.sv line 104 should work for hammerblade-example?

[Dan Petrisko]

Hi,

It’s not a super useful feature in this context. You should just edit the configs in bp_common_pkg if you need to

But, for clarity. The ‘define flow was designed to support sweep testing configurations without modifying the file itself:

 So you would point the ‘BP_CUSTOM_CFG to a base configuration and then ‘BP_PADDR_WIDTH to a custom value, for example

Best,

-Dan

To view this discussion visit https://groups.google.com/d/msgid/black-parrot/77b8e2f4-12c0-4ae2-b684-c4204f3705f6n%40googlegroups.com.

[Ruchita]

Hi Dan,

In bp_common_pkg.sv I made following changes for hammerblade example::

bp_unicore_hammerblade_cfg_override_p =
    '{cc_x_dim  : 2
      ,cc_y_dim : 2


parameter bp_proc_param_s [max_cfgs-1:0] all_cfgs_gp =
  {

 // ,e_bp_custom_cfg                                = 1
    ,e_bp_unicore_hammerblade_cfg_override_p = 1


typedef enum bit [lg_max_cfgs-1:0]
  {
 
   // ,e_bp_custom_cfg                                = 1
    ,e_bp_unicore_hammerblade_cfg_override_p = 1

In Makefile.design
CFG ?= e_bp_unicore_hammerblade_cfg_override_p

then I did make simv

It is hanging at this stage:

Warning-[V2KGFLUCTL] Unroll count may be too large
zynq-parrot/import/basejump_stl/bsg_misc/bsg_mux_one_hot.sv, 18
  Generate for loop unroll count may be too large.
  May be an infinite loop.


Warning-[V2KGFLUCTL] Unroll count may be too large
zynq-parrot/import/basejump_stl/bsg_misc/bsg_mux_one_hot.sv, 18
  Generate for loop unroll count may be too large.
  May be an infinite loop.


Warning-[V2KGFLUCTL] Unroll count may be too large

zynq-parrot/import/basejump_stl/bsg_misc/bsg_mux_one_hot.sv, 18
  Generate for loop unroll count may be too large.
  May be an infinite loop.

I want to change single core to dual core or any n core, so I did this:

cc_x_dim  : 2

 ,cc_y_dim : 2

Am I doing correct changes?

Regards,

-Ruchita

[Dan Petrisko]

The hammerblade example is designed for 1 BP and will need significant modification to support a larger multicore. 

Best,

-Dan

To view this discussion visit https://groups.google.com/d/msgid/black-parrot/c36a901a-a801-465d-b191-dd4ccf9be429n%40googlegroups.com.

[Ruchita]

I am curious to know why hammerblade example not supported for multicore BP? I  understand considering zynq FPGA fabric is not large enough to fit this design but one might try  for vcs simulation and ASIC implementation. 

I found this git repo: https://github.com/bespoke-silicon-group/hb_bigblade/tree/master which does support multicore but this repo 5 years old, I tried to clone it and build  but https://bitbucket.com/taylor-bsg link is dead. 

Regards,

-Ruchita

[Dan Petrisko]

There’s no technical reason it couldn’t be done. The version actually taped out in 12nm silicon, (hb_bigblade) and 28nm silicon (maxSDR) ended up being unicore so the FPGA example reflects that completed work

I would like to support the multicore fabric but there are many ways it could be integrated (coherence at the L2, coherence at the L1, unified L3 with manycore) and those comparative analyses have not been done yet

Which taylor-bsg repo is it trying to pull from? I think the relevant ones should be public but we can update any dead links

Best,

-Dan

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[Ruchita]

These are the links:

https://bitbucket.com/taylor-bsg/bsg_cadenv
 https://bitbucket.com/taylor-bsg/board
 https://bitbucket.com/taylor-bsg/bsg_packaging

I guess they are not public because when I clone it is asking username and password.

[Dan Petrisko]

 https://bitbucket.com/taylor-bsg/board
 https://bitbucket.com/taylor-bsg/bsg_packaging

are both public bitbucket repos, but you may need to set an ssh key if it's doing an ssh clone. 

bsg_cadenv is not necessary; it is used to set up the CAD tools on our BSG servers. You can just create a directory bsg_cadenv/cadenv.mk and populate that with any relevant paths (VCS_HOME, LM_LICENSE_PATH, etc.)

Best,

-Dan

To view this discussion visit https://groups.google.com/d/msgid/black-parrot/b689de0c-53d4-4db7-af9a-0058d237a5cbn%40googlegroups.com.

[Ruchita]

Thanks. Have you implemented hb_bigblade in any FPGA for multicore?  I looked at this repo: https://github.com/black-parrot-examples/bsg_fpga I guess this repo is for BP.

[Ruchita]

I am wondering,  supporting multicore fabric at: coherence at the L2, coherence at the L1, unified L3 with manycore) and  conduct comparative analyses could be research topic for me. Can  you provide me which files, papers to look?

Regards,

-Ruchita

[Dan Petrisko]

Hi Ruchita,

bsg_14 is the BSG proprietary CAD flow, you’ll have to supply your own for ASIC implementation. 

I’d say these (and the citations) are the most relevant for large manycores in this class:

https://www.csl.cornell.edu/~zhiruz/pdfs/hammerblade-isca2024.pdf

https://arxiv.org/abs/2008.06502

https://www.bsg.ai/papers/BlackParrot_IEEE_Micro_2020.pdf

Best,

-Dan

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[Ruchita]

Thanks I will look at the papers.  The repo: https://github.com/bespoke-silicon-group/hb_bigblade/tree/master   says    "This repository contains the release candidate designs for the HammerBlade "Big Blade" tape-out, taped out as a Global Foundries 12nm 100mm^2 SoC in March 2020, which contains 2048 compute-optimized RISC-V cores and 8 Linux capable cores"  In FPGA work, this work presents one linux capable core and one  compute-optimized RISC-V core?  If so, the FPGA work can be scaled to  8 Linux capable cores and  2048 compute-optimized RISC-V cores ?

[Dan Petrisko]

The cores are independent single cores attached to each manycore pod, 2 BP per 128 MC pod. 

To view this discussion visit https://groups.google.com/d/msgid/black-parrot/2a45e374-221b-43a5-9a66-93cfe59568a7n%40googlegroups.com.

[Ruchita]

So  e_bp_unicore_hammerblade_cfg in FPGA is singe BP core per single MC?  Or 2 BP core  per 128 MC pod? I was looking at source codes, where BP and manycore are interfaced, I found this source code: https://github.com/black-parrot-hdk/black-parrot-subsystems/blob/cf7b159608ed557c74eea9828612188e59705e7a/manycore/v/bsg_hammerblade.sv 
I guess if I want to support multicore, I may need to modify this source code? 

and 

this link https://github.com/black-parrot/black-parrot/blob/master/docs/bedrock_guide.md explain to interface BP with coherent accelerator, I guess same technique could be used for bsg_hammerblade.sv ?