Requesting GSOC and Open-source contribution tips

[Aditya Nukala]

Dear Team,

I am Aditya , a recent Master's graduate in Computer Engineering. I am a newbie in open-source development . I am very much interested in the field of Design Verification(SystemVerilog, UVM) so I would like to gain some real world experience by contributing. I have seen this repo in the FOSSi webpage regarding UVM Testbenches. So I would like to know your current focus on any particular module for verification and also requesting some tips for a newbie.

Regards,

Aditya

[Dan Petrisko]

Hi Aditya,

I recommend starting with a simple, combinational module like the ALU. I think for the summer, a complex module like the I-cache would be a solid goal. This is a great starting point if you have no UVM experience: https://www.amazon.com/SystemVerilog-Verification-Learning-Testbench-Language/dp/1461407141

Best,

-Dan

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