Hammerblade+BP

[Julio Sanchez]

Hi,

I am a PhD student in Spain. I was studying black-parrot-sdk repo and bsg_manycore repo. I am unable to locate some examples of BP+Manycore in black-parrot-sdk repo, I am looking some software examples of integrating BP many core CPUs and GPGPU (BSG Manycore) examples,  can you please point me such examples? If there are no examples, is the Manycore Base address defined like below?

#define MC_Y_DIM bp_param_get( PARAM_MC_Y_DIM )

#define MC_BASE_ADDR (uint64_t *) ((uint64_t) (BP_CONFIG+ MC_Y_DIM)<<BP_CFG_WIDTH)

 as shown in  https://github.com/black-parrot-sdk/bp-tests/blob/d56ddc8d6f6ec4ca821075df2e5bb8d30d9f7bac/src/vdp.h line #7-11

If the MC_BASE_ADDR calculation is right, then bsg_replicant libraries can be used as cuda-lite libraries to interface BP,  like one example: https://github.com/bespoke-silicon-group/bsg_replicant/blob/e952023cc498c54a26a9c828ae1c3843b133cc68/examples/cuda/test_float_vec_add/main.c  ?  In this case, MC_BASE_ADDR is used as port address access manycore?

Muchas Gracias,

Julio

[Dan Petrisko]

Hi Julio,

Currently, the software support is only for a single BP host core + manycore, even when the BP is part of its own multicore system. The default host interface is a non-blocking FIFO array (host request, device response, device request, host response). This is what the bsg_replicant / CUDA-lite libraries support (since the original usage was x86 host over PCIE, much like GPGPU). BP also has a direct-mapped MMIO command interface similar to DMA. There is very little documented support for this at the moment, although we have used it in real chips in the past so it should work pretty reliably

>If the MC_BASE_ADDR calculation is right, then bsg_replicant libraries can be used as cuda-lite libraries to interface BP

Yep, there are some examples of doing so in this patch series:

https://github.com/bespoke-silicon-group/bsg_replicant/pull/826

https://github.com/bespoke-silicon-group/bsg_replicant/pull/827

https://github.com/bespoke-silicon-group/bsg_replicant/pull/828

Let me know if you have any questions; I'm happy to help

Best,

-Dan

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[Julio Sanchez]

Hello Dan,

Thanks for the brief explanation. I was going through MMIO function calls, I found this code: https://github.com/bespoke-silicon-group/bsg_replicant/blob/bcd579efc0004de3e3223d69fafabcb2f60d3806/libraries/platforms/deprecated/aws-fpga/bsg_manycore_mmio.cpp  line no 103-142, hb_mc_mmio_read(), line #152-191, hb_mc_mmio_write(),  I think running sample application like: https://github.com/bespoke-silicon-group/bsg_replicant/blob/bcd579efc0004de3e3223d69fafabcb2f60d3806/examples/cuda/test_float_vec_add/main.c

in BP+Manycore is pretty straightforward,  considering   MC_BASE_ADDR is the manycore address, the only place one need to change in hb_mc_mmio read () from line #122 to  #124 with 

addr =  (int*)MC_BASE_ADDR; 

// by de referencing addr, like *addr, one will get read value

in hb_mc_mmio_write(), line 171-184 replace with 

int val;

addr = (int*) MC_BASE_ADDR  ;
   *addr = val; // assuming that one writing 32  bit value

Since BP +Manycore core is on the same fabric, I guess running thee above  test_float_vec_add/main.c in BP should work?

Muchas Gracias,

Julio

[Julio Sanchez]

Hello Dan,

I hope you are doing fine. For bsg_manycore accelerator to pass data between ps.cpp and bsg_manycore is through dram, after line #146: https://github.com/black-parrot-hdk/zynq-parrot/blob/master/cosim/manycore-example/ps.cpp one would assign value to DRAM memory like:

 int *address;
 address = (int*)phys_ptr;

 *address = 0xDEADBEEF;

in bsg_manycore, one would read the value like:

 #define address 0x80000000
 bsg_printf("address val= %x\n", *read_address);

Is this correct way?

Julio