Config BlackParrot flash on VC707 FPGA

[Lap Dang]

Hi team,

I just clone git: https://github.com/black-parrot-hdk/zynq-parrot and run make_file to build bitstream. I am newbie and I have some questions:

1. Where the location will save the output file after build done?

2. Can you share a guideline to config on VC707 board, I tried change 'bp_axi_top' but failed. Pls give a help. Thank you.

---

Best,

Lap

[Daniel Petrisko]

Hi Lap,

1) to build bitstream, you should be the “vivado” directory of whichever example you are building. The outputs will be there in the standard vivado folders (.runs, etc)

2) you should not have to modify RTL. The tcl script in the vivado directory is board and vivado version specific, so you will have to look at the existing script and modify it for your board. It should not be a large change, but vivado tends to change properties, parameters and defaults between versions

Best,

-Dan

On Apr 12, 2024, at 11:01 PM, Lap Dang <lap...@gmail.com> wrote:

Hi team,

--
You received this message because you are subscribed to the Google Groups "black-parrot" group.
To unsubscribe from this group and stop receiving emails from it, send an email to black-parrot...@googlegroups.com.
To view this discussion on the web visit https://groups.google.com/d/msgid/black-parrot/f23fc275-7bfb-488c-b783-52f64d7f002an%40googlegroups.com.