That's interesting. If it works in VCS and not hardware that's a bit trickier to debug. (don't worry about dromajo, that's for if VCS doesn't work). As first steps, I would:
- check for any critical warnings during bitstream generation
- print out AXI DRAM traces in VCS simulation. I don't think there's a builtin way to do this right now, but you can trivially add prints to the module itself
- put an ILA tracer on the AXI DRAM accesses
- make sure the DRAM traces match
- Do the same thing for PC of BlackParrot which is in the path <path_to_core>/core_minimal/be/calculator/pipe_sys/csr/apc_r
Best,
-Dan