Digital Logic With Vhdl Design
Sheila Cast
Hello, I am very new to mixed signal simulation using cadence virtuoso. I want to simulate a design which includes an ADC(analog) and a digital logic. The digital part of the design includes blocks written in verilog as well as VHDL.
I created a config view and imported all the digital design files. I use functional view for the verilog files but not sure which view to use for VHDL as these files are listed as behav and entitiy views.
My apologies - you edited the post after the email notifier was sent (I believe) because the statement about how you imported wasn't in the email, and I didn't notice it on the web page when I answered.
Strange - I didn't get that yesterday, but maybe one of my intermediate steps generated the pc.db at the time I imported the design. Not sure. I then created an hdl.var file in the working dir and opened the config again. The hdl.var contains:
I still got the messages about the entity requiring re-analysis. This is possibly because I switching XCELIUM versions in the middle of my tests to pick something closer to you, so I imported with a different version to the one you're using. So I opened each entity view and then hit the "check-and-save" icon (a save icon with a green tick on it). Having done that I can then open the config and all is OK - the pc.db gets regenerated.
Fundamentals of Digital Logic with VHDL Design is intended for an introductory course in digital logic design, which is a basic course in most electrical and computer engineering programs. A successful designer of digital logic circuits needs a good understanding of the classical methods of logic design and a firm grasp of the modern design approach that relies on computer-aided design (CAD) tools. The main goals of this book are to teach students the fundamental concepts of classical manual digital design and to illustrate clearly the way in which digital circuits are designed today, using CAD tools.
This title will be available in Connect. Its Connect shell consists of the MHeBook, Tegrity, Proctorio, and the ability to add your own questions. It does not have SmartBook or assessment in the question banks.
1 L'algebra di Boole
2 Circuiti digitali combinatori
3 Circuiti digitali sequenziali
4 Progettazione di Circuiti Digitali tramite Macchine a Stati Finiti
5 Introduzione al VHDL (Very High Speed Integrated Circuits Descritpion Language)
6 Circuiti combinatori e Sequenziali in VHDL
7 Progettazione di Circuiti digitali in VHDL
8 Programmazione di FPGA
Operatori e Componenti Logici
o Operatori Logici Elementari, Teoremi di De Morgan e del Consenso
o Sintesi Combinatoria attraverso Sum-of-Products e Product-of-Sums
o Mappe di Karnaugh , Alee Statiche e Dinamiche
Il VHDL come Linguaggio di Descrizione Hardware
o Dispositivi Logici Programmabili e Dedicated CMOS Design (ASIC)
o VHDL. Un semplice esempio di progetto
o Dichiarazione di Entity e Architecture. Assegnazioni e Istruzioni concorrenti
o Il process in VHDL
The course target is giving the knowledge necessary to solve the control and the design of interfaces between external world and internal eleboration unit, analyzing and comparing different hardware and software solutions based on the use of microcontrollers. At the end of the course the students will be able to develop an embedded application using a microcontroller and designing digital logic circuits, debugging them by means of simulations using a specific HDL software
The aim of the course is to provide the skills needed for digital circuits design on programmable hardware. At the end of the course, students will be able to independently develop an embedded application using an FPGA and designing digital logic circuits, performing simulation-level debugging, and using specific software for circuit simulations designed through Hardware Description Languages.
Logic Operators and Logical Components
o Basic Logical Operators, De Morgan and Consensus theorems
o Combinatory Synthesis by Sum-of-Products or Product-of-Sums
o Karnaugh Maps, Static and Dynamic Hazards
The VHDL as Hardware Description Languages: an Overview
o Programmable Logic Devices, Dedicated CMOS Design (ASIC)
o VHDL. A simple design example
o Entity Declaration. Architecture Declaration, Assignments, Concurrent Statements
o The Process
Lectures for basic concepts. Classroom exercises with the presentation and discussion of digital circuits in VHDL/Verilog. Laboratory activity for the development of digital circuits and for the use of FPGAs in simple applications
The course will be held in Italian.
The score assigned to each part is 15/30 each.
In the first part the student will present documentation and functionalities of a specific hardware system developed entirely by the same student and related to a project topic assigned in class to groups consisting of at most two students.
In the second part, the examination of the student will take place through two questions related to the topics covered during the course, and in particular the first one concerning the combinatory circuits and a second on the sequential circuits.