Register Compare Immediate under Mask

[indust...@winwholesale.com]

        Is there an assembler mnemonic to compare an immediate under mask against a register?  Meaning, I want to individually test the lower two bytes of a register for return code and feedback information.  Something like the following.  I've been looking through the PoOp manual but nothing so far.  I know I could store characters under mask and then compare logical immediate, but I'd rather not have to do that.  Is this possible?


IF   R15,(EQ,TM,B'0010'),$MXR00   IF RC = OK              
AND  R15,(EQ,TM,B'0001'),$MX00IG  BUT NOTHING SPOOLED, YET
 XR  R15,R15                      IGNORE THAT RETURN CODE
ENDIF                                                    


Sincerely,

Dave Clark
--
Winsupply Group Services
3110 Kettering Boulevard
Dayton, Ohio  45439  USA
(937) 294-5331



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[David Stuart]

Hi Dave, 

I find a Compare Halfword Immediate (CHI) that looks like it uses a register. Not sure, off hand, which 'way' it 'goes'. 

And there's CLM, and CLI, but I believe you would need to store the register value, first.

But I don't find any 'immediate' compares for/using a register, except CHI. 

Dave 

Dave Stuart

Principal Info. Systems Support Analyst

County of Ventura

805-217-2413

David....@ventura.org

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[indust...@winwholesale.com]

"VSE-L" <vse-l-bounces+industrynews=winwhole...@lists.lehigh.edu> wrote on 08/25/2021 03:07:13 PM:
> I find a Compare Halfword Immediate (CHI) that looks like it uses a
> register. Not sure, off hand, which 'way' it 'goes'. 
>
> And there's CLM, and CLI, but I believe you would need to store the
> register value, first.
>
> But I don't find any 'immediate' compares for/using a register, except CHI. 

        Yes, I could use CHI if I wanted to compare both low-order bytes at the same time.  I may do that.  I did find TMH and TML but that does bit testing rather than a straight compare.

[Tony Thigpen]

Dave,

I don't think you will see anything in the high-half of R15. If you do
see something in the high-half, then it's an error anyway.

try:
CHI R15,4
BH *+4+2
XR R15,R15




Tony Thigpen

David Stuart wrote on 8/25/21 3:07 PM:

> Hi Dave,
>
> I find a Compare Halfword Immediate (CHI) that looks like it uses a
> register. Not sure, off hand, which 'way' it 'goes'.
>
> And there's CLM, and CLI, but I believe you would need to store the
> register value, first.
>
> But I don't find any 'immediate' compares for/using a register, except CHI.
>
>
> Dave
>
>
> Dave Stuart
>
> Principal Info. Systems Support Analyst
>
> County of Ventura
>
> 805-217-2413
>

> David....@ventura.org <mailto:David....@ventura.org>

> VS...@lists.lehigh.edu <mailto:VS...@lists.lehigh.edu>
> https://lists.lehigh.edu/mailman/listinfo/vse-l
> <https://lists.lehigh.edu/mailman/listinfo/vse-l>

[Mick Poil]

CHI compares the whole register and is faster than the older CH since no storage is accessed because the signed 2nd operand binary value is already in the instruction cache.

CLM is a way to compare 1 to 4 bytes of the register *logically* against storage.

They are very different as is TMH etc.

[indust...@winwholesale.com]

"VSE-L" <vse-l-bounces+industrynews=winwhole...@lists.lehigh.edu> wrote on 08/25/2021 04:07:45 PM:
> CHI compares the whole register and is faster than the older CH
> since no storage is accessed because the signed 2nd operand binary
> value is already in the instruction cache.

        As an aside...  I noticed in the IPWSEGM expansion it uses SR to zero a register where I always use XR.  Which should I really be using?   ;-)

[David Stuart]

For some reason, and I can't tell you why, I've always been under the impression that XR was marginally faster than SR. But at the speed of today's processors, I really don't think it matters. Except maybe in some very special circumstances. 

Dave 

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[indust...@winwholesale.com]

"VSE-L" <vse-l-bounces+industrynews=winwhole...@lists.lehigh.edu> wrote on 08/25/2021 04:29:00 PM:
> For some reason, and I can't tell you why, I've always been under
> the impression that XR was marginally faster than SR.

        That is my impression as well.

> But at the speed of today's processors, I really don't think it
> matters.

        That is also my feeling but if I know for sure that one is faster, I would like to do it that way.

[K and M]

Load half word immediate of zero could possibly be faster than both.  :)
 
Ken
 
 
 

snip..

[indust...@winwholesale.com]

"VSE-L" <vse-l-bounces+industrynews=winwhole...@lists.lehigh.edu> wrote on 08/25/2021 04:50:23 PM:
> They all are likely to use one CPU cycle.
> You missed LA Rn,0.


        But LA and LHI are 4-byte instructions.  I prefer the shorter instructions where feasible.

[Jeffrey Barnard]

Dave,

For the best way to clear/zero a register I would look at what the latest
compilers do. I would expect SR or perhaps LHI. Still I could be wrong. I
would to avoid memory references (L Rx,=F'0') and register interlocks.

The kicker here is to place the instruction after a memory reference
instruction. By doing this it will run at the same time as the memory
reference instruction. Thanks out of order/speculative execution! Might
even end up with effectively a zero execution time.

Compilers will do work optimizing to arrange instructions in the best way
so that processor can get the most work done. I do not expect any z/VSE
compiler to generate properly optimized code for z13 and newer processors,
z/VSE compilers are far to old. However, the zLinux, z/OS and z/VM
compilers are newer and much better at this.

Regards,
Jeff

[Jeffrey Barnard]

Dave Rivers of the Dignus C compiler fame wrote this to me ...

To conclude, the LHI and LGHI are probably the best overall
instructions for clearing a register on any generation processor.
I can not imagine we would ever design a machine where these
instructions were not at least as fast as XR/SR/SLR for clearing
a register, and they have some benefits on prior models.


Jim Mulder z/OS System Test IBM Corp. Poughkeepsie, NY

So, I will probably adjust my programming ...

[Andy_S...@hm-software.com]

>> To conclude, the LHI and LGHI are probably the best overall instructions
for clearing a register on any generation processor. <<

The word "any" probably should be taken with a shaker of salt. In the
context of recent processor models that's probably true - but I believe
LHI/LGHI only became available in later instruction sets.

>> I can not imagine we would ever design a machine where these instructions
were not at least as fast as XR/SR/SLR for clearing a register <<

Way beyond my expertise. Let me just point out the difference in instruction
length. Even if they execute equally fast, I don't know if nowadays there
are still differences in FETCHING an instruction relative to length.

[Jeffrey Barnard]

On 8/26/21 8:33 AM, Andy_S...@HM-Software.com wrote:
> The word "any" probably should be taken with a shaker of salt. In the
> context of recent processor models that's probably true - but I believe
> LHI/LGHI only became available in later instruction sets.

Immediate and Relative instructions have been around for quite a while.
Since 9672 G5 at least. That's 1998, so 23+ years. Any IBM zSeries and
later will have them. Pretty safe to use them these days.

[Andy_S...@hm-software.com]

Gosh - time flies.

I suppose I should make time to upgrade from Windows 2000  😉.

 

-----Original Message-----
From: VSE-L <vse-l-bounces+andy_schmidt=hm-soft...@lists.lehigh.edu> On Behalf Of Jeffrey Barnard
Sent: Thursday, August 26, 2021 8:52 AM
To: vs...@lists.lehigh.edu
Subject: Re: Register Compare Immediate under Mask

 

On 8/26/21 8:33 AM, Andy_S...@HM-Software.com wrote:

[Mick Poil]

I feel we are in danger of "straining at gnats".  I think you would need to look at z/OS compiler output optimised for the z13/14/15 to get any sense of what is the modern way to do things. 15 years ago I worked on the z/OS Java JVM which was mostly C code and it was extremely efficient to the extent that is was often almost impossible to debug at the object code level. The object code created by VSE compilers is probably not that much better than System/370 standard.

Mike

[indust...@winwholesale.com]

"VSE-L" <vse-l-bounces+industrynews=winwhole...@lists.lehigh.edu> wrote on 08/25/2021 04:43:38 PM:
> Load half word immediate of zero could possibly be faster than both.  :)

        Thanks.  Even though the instruction is 2 bytes longer, I do like how the LHI instruction looks both for being intuitive as well as for consistency because it can be used to set non-zero values as well.  Thus, I won't be using two different instructions for basically the same thing -- XR/SR for return code 0 and LA for non-zero return codes.  Yes, LA can be used for both, but how "intuitive" is LA when you're not really loading an address?  ;-)


IF    R1,(EQ,CR),R15,OR,PARMLENG,(NH,CLC),=H'15'          
 LHI  R15,16                   MISSING OR INVALID PARM      <===
ELSE                          ELSE                        
 LA   R2,PARMUNIT              SET ADDR OF LOGICAL UNIT  
 LA   R3,PARMJECL              SET ADDR OF JECL STATEMENT
 LH   R4,PARMLENG              GET PARMS LENGTH          
 SH   R4,=H'7'                 SUBTRACT UNIT AND DELIM LEN
 IPWSEGM DEVADDR=(2),KEEP=YES,JECL=(3),JECLN=(4)          
 IF   R15,(EQ,CHI),X'0004'     IF RC=OK BUT NO OUTPUT YET
  LHI R15,0                     IGNORE THAT RETURN CODE     <===
 ENDIF                                                    
ENDIF                         ENDIF                      

Sincerely,

Dave Clark
--
Winsupply Group Services
3110 Kettering Boulevard
Dayton, Ohio  45439  USA
(937) 294-5331

> Ken

>
> snip..

>
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[Carl Edwards via VSE-L]

Agree.


Sent from Yahoo Mail for iPad

On Thursday, August 26, 2021, 9:14 AM, Mick Poil <michael...@gmail.com> wrote:

I feel we are in danger of "straining at gnats".  I think you would need to look at z/OS compiler output optimised for the z13/14/15 to get any sense of what is the modern way to do things. 15 years ago I worked on the z/OS Java JVM which was mostly C code and it was extremely efficient to the extent that is was often almost impossible to debug at the object code level. The object code created by VSE compilers is probably not that much better than System/370 standard.

Mike

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[K and M]

Since threading of instructions has been mentioned, the SH following the LH makes logical sense, 
but it now means the SH has to wait until the LH has been processed. ;) The speed of the new 
machines is based on how many threads can be used at the same time, referring to the out of
order instruction processing possible.
 
Ken
 
 
 

snip..

 LH   R4,PARMLENG              GET PARMS LENGTH          
 SH   R4,=H'7'                 SUBTRACT UNIT AND DELIM LEN
 IPWSEGM DEVADDR=(2),KEEP=YES,JECL=(3),JECLN=(4)          
 IF   R15,(EQ,CHI),X'0004'     IF RC=OK BUT NO OUTPUT YET
  LHI R15,0                     IGNORE THAT RETURN CODE     <===
 ENDIF                                                    
ENDIF                         ENDIF                      

snip..

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