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The IoT market presents semiconductor vendors with several new challenges. One size does not fit all, with each market requiring a cost-effective and performance-optimized solution. Quite simply the market size in any one area does not generate a sufficient Return on Investment (ROI) to justify the investment. Another issue in the name of flexibility is that often equipment (and hence the chips within) need frequent updating, either for software upgrades, bug fixes or for provisioning of new services. While the media, Wi-Fi, Bluetooth, or ZigBee etc. exists the real issue is to ensure that this is done securely, that the user has valid access privileges and that these privileges are kept secure. While security aspects of semiconductors are not new it has only really been a luxury afforded by high-end systems safety or security critical systems. A typical IoT endpoint is typically not a complex, high-performance part and needs to be manufactured at very low cost (basically a sensor, controller and wireless interface). With the proliferation of IoT nodes, just about any end point in the IoT network can present a security vulnerability. Moreover, some of these end nodes are not in office buildings or behind firewalls, but in the field (literally) and many may be left unattended 24/7, giving determined hackers plenty of access time. The final, and quite significant, pain point is the increasing issue of counterfeiting. While, for suppliers, this presents itself as potential lost revenue; for the end user (through the use of inferior products) it presents safety and reliability issues.
Intellitech has taken this concept further in creating a Silicon Instrument which uses the IEEE 1149.1-2013 languages to describe fab, wafer, unique ID, die X-Yposition, speed and temperature grade along with the pass/fail status of the die and an optional 256-bit HASH of this data.
Sidense Integrated Power Supply macrocells (IPS) are designed to supply read (VRR) and programming voltages (VPP) for the Sidense memory array. This modular IPS design includes several circuit blocks, including a reference generator, a regulator with standard output, a regulator with high output power driver and a regulated charge-pump for in-field programming. In more recent designs temperature compensation is built into the IPS to prevent attacks through temperature manipulation.
The Sidense controller is an RTL block interfacing with the OTP memory array and the Integrated Power Supply (IPS). The controller integrates three main functions: a BOOT function for OTP and IPS power-up, a PROGRAM function for programming and verifying the memory array, and a built-in self-test (BIST) array with defect repairs. It also provides data protection for the OTP content with a built-in Hamming Error Correction Code (ECC) and bit repair circuit.
In addition to the security features inherent in the antifuse bit-cell, additional security features may be made available via the controller. These include built-in redundant and/or differential read modes that provide high read margins over a wide operating voltage and temperature range to prevent tampering using ambient conditions. There is also a built-in read timer to prevent tampering with clock cycles and hidden OTP test rows. In selected designs delayering protection techniques, including routing to disable access with partial metal removal, are used.
1T-NVM provides designers with a lot of flexibility, allowing the NVM areas to be allocated for many uses over and above ECID. For example, a 64 Kbit (65,536 bits) memory could be used, where the top 1 Kbits (1,024 bits) are used for ECID and die information while the remaining 64,512 bits could be used for other NVM uses such as secure boot code, configuration settings and security keys. A portion of this memory could also operate as eMTP or be converted to ROM.
The Intellitech ECID Silicon Instrument comes complete with IEEE 1149.1-2013 compliant descriptions for use with the IEEE 1149.1 JTAG TAP. The new IEEE 1149.10-2017 standard builds upon the Design-for-Test and languages of 1149.1 but removes the JTAG TAP and allows other mission-mode interfaces for test access such as SERDES and SPI (Serial Peripheral Interface). PMICs (Power Management ICs) and ADC/DACs may be devices which can benefit from NVM for trim settings but are not likely to have an IEEE 1149.1 TAP controller. They do typically incorporate SPI, which can be used to access the NVM in the same manner as JTAG.
Using the same PDL operations used in verification, NEBULA can generate STIL or WGL patterns for use on traditional ATE. A low-cost USB-based JTAG/SPI controller is available for NEBULA, which can be used for working with the IC in-situ (within the system) during silicon debug, characterization, lab programming or in-the-field programming of the NVM.
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