On Fri, 28 May 2021 10:11:46 -0700 (PDT), in
gmane.comp.hardware.beagleboard.user Bruce Chidester
>Thanks for your response.
>When developing with the UIO architecture, they use the term "interrupt",
>so I assume they meant it somehow, but not willing to die on that hill. I
>could not get any form of "what they called interrupt" to work the remote
>proc architecture. I tried, and tried, and tried. If that solution exists I
>would greatly appreciate it.
I'd need to study much more to find out how a PRU passes an interrupt
to the ARM core, but a comment in
(getting started guide from TI: SPRACE9A)
The PRU_ICSSG adds a Task Manager, which can preempt currently running
code. The Task Manager allows firmware to meet timing requirements for high
priority tasks by interrupting lower priority tasks.
reinforces that the non-enhanced PRUs on the BBB (PRU_ICSS vs PRU_ICSSG) do
not have preemptive interrupts.
That document also implies that interrupts are viable, but have to be
defined in the resource tables of the firmware
User applications can require communication between the PRUs and the Arm
core. Linux provides a method for this communication called RemoteProc
Messaging (RPMsg). RPMsg fits into the RemoteProc framework. TI provides a
RPMsg library and getting started examples to demonstrate how to use RPMsg.
These examples showcase the PRU firmware using its resource table to
request specific interrupt mappings and shared memory to implement the
Strangely, section 126.96.36.199 of
describes TI's PRU as Ethernet port mode, supposedly using RProc/RPMsg. But
when you get to the Linux side (section 188.8.131.52) they are suddenly back to
) indicates that PRU interrupt #60 is
the one that "sets" when a message has been left in the PRU0 mailbox.
SPRUHF8A (am335x Pru Reference) has
The PRU-ICSS interrupt controller (INTC) is an interface between interrupts
coming from different parts of the system (referred to as system events)
and the PRU-ICSS interrupt interface.
The PRU-ICSS INTC has the following features:
• Capturing up to 64 System Events
• Supports up to 10 interrupt channels.
• Generation of 10 Host Interrupts
– 2 Host Interrupts for the PRUs.
– 8 Host Interrupts exported from the PRU-ICSS for signaling the
ARM interrupt controllers.
• Each system event can be enabled and disabled.
• Each host event can be enabled and disabled.
• Hardware prioritization of events.
• Host Interrupt 0 is connected to bit 30 in register 31 of PRU0 and
• Host Interrupt 1 is connected to bit 31 in register 31 for PRU0 and
• Host Interrupts 2 through 9 exported from PRU-ICSS for signaling ARM
interrupt controllers or other machines like EDMA.
Unfortunately, I've never found any documents for either RPMsg or UIO
APIs... Or, at least, not something I'd consider API documentation (I was
spoiled decades ago by the documentation for VAX/VMS, which filled two
shelves of a bookcase with 3" 3-ring binders).
Dennis L Bieber