Hello.
I am quite new to PRU, sorry in advance if I make any mistake or incorrect asumption.
I would need to read a LVDS signal which is a 4 data channels + CLK and Framesync, that looks like this:
As you can see, the signals change in every edge (both falling and rising edges).
Of course, we would place a differential LVDS driver receptor prior to the beaglebone pru ports (so signal will be exactly as the black + traces in the figure). Our intention is to send them later to memory and probably the ARM would create a UDP packet to send them over ethernet.
I would like to know if there is a way to receive these signals with the PRU in any way and process them correctly.
Would it be a Direct Connection Mode configuration?
If not would it be possible to make a fast polling on the CLK & FRAME signals, and in every change read/sample the other 4 channels simultaneously?
Thank you all.
You don’t indicate how fast your clock is. Everything in the PRU is polled, so you would have to construct a loop that looks at each pin and makes a determination if the clock has changed state. The PRU operates at 200 MHz and has simple instructions, so you would have to calculate how many instructions you have for each clock to determine if it is even possible. Then, of course, you have to put the data somewhere. Typically one PRU is used to poll I/O lines and assemble the data into chunks that are passed to the 2nd PRU which can either put them in ARM DDR memory, send out, etc. If you get the voltages on the PRU input pins correct and the data rate is within what the PRU can handle, then this can be done.
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Our signal will be in the tens of MHz (from 5Mhz to 50MHz max), depending on configuration.The polling method is what I expected, however the manual (spruh73q) states there are three methods (Direct Input, Parallel Mode and 28bit shift Register), which confuses me. In your proposal, is Direct Input used? What is the max speed at this mode, 100MHz?What is the difference between using Parallel mode and Polling, the automatic clocking?
#define CLKB 5 // define the clock bit# for polling
...
LDI r0, 0 // counter init
HIGH:
QBBC r31, HIGH, CLKB // wait for clk bit getting high
SBBO r31, r0, 0, 2 // safe data
ADD r0, r0, 2 // increment counter
QB?? ??, OUT // termination
LOW:
QBBS r31, LOW, CLKB // wait for clk bit getting low
SBBO r31, r0, 0, 2 // safe data
ADD r0, r0, 2 // increment counter
QB?? ??, HIGH // reverse termination
OUT:
// Note:
// In order to get higher frequency the SBBO + ADD instructions can
// get replaced by MVIW for buffering the data in the register file,
// but this is limited to 30*2=60 sets of data.
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My idea is to create a simpler, better device able to work with the beaglebone (or the beaglewire), allowing users to create their own radar applications in a very fast way (including the UI).
My idea is to create a simpler, better device able to work with the beaglebone (or the beaglewire), allowing users to create their own radar applications in a very fast way (including the UI).
Methinks that the BBB can have a SRAM-like 16 Bit bus interface. That
would be
very interesting for FPGA device registers, FIFOs, DMA buffers and such.
Reasonably wide single cycle acesses, but I'm not sure what has to be
given up for it, ...