Beaglebone AI UART access

[ahni...@gmail.com]

Hello.

I am wondering if some one can access UART on Beaglebone AI. I updated *.dts file so I think I got /dev/ttyS1, ttyS2, ttyS3, ttyS4 and ttyS5 on my kernel.

 debian@beaglebone:/dev$ ls -al ttyS*

crw------- 1 debian tty     4, 64 Mar 13 01:04 ttyS0

crw-rw---- 1 root   dialout 4, 65 Mar 12 22:23 ttyS1

crw-rw---- 1 root   dialout 4, 66 Mar 12 22:23 ttyS2

crw-rw---- 1 root   dialout 4, 67 Mar 12 22:23 ttyS3

crw-rw---- 1 root   dialout 4, 68 Mar 12 22:23 ttyS4

crw-rw---- 1 root   dialout 4, 69 Mar 12 22:23 ttyS5

debian@beaglebone:/dev$ dmesg | grep tty

[    0.000000] Kernel command line: console=ttyS0,115200n8 root=/dev/mmcblk1p1 ro rootfstype=ext4 rootwait coherent_pool=1M net.ifnames=0 rng_core.default_quality=100 quiet

[    0.931970] console [ttyS0] disabled

[    0.932020] 4806a000.serial: ttyS0 at MMIO 0x4806a000 (irq = 43, base_baud = 3000000) is a 8250

[    1.018956] console [ttyS0] enabled

[    1.019768] 48020000.serial: ttyS2 at MMIO 0x48020000 (irq = 44, base_baud = 3000000) is a 8250

[    1.020527] 48066000.serial: ttyS4 at MMIO 0x48066000 (irq = 45, base_baud = 3000000) is a 8250

[    1.021268] 48068000.serial: ttyS5 at MMIO 0x48068000 (irq = 46, base_baud = 3000000) is a 8250

[    1.021996] 48422000.serial: ttyS1 at MMIO 0x48422000 (irq = 47, base_baud = 3000000) is a 8250

[    1.022744] 4ae2b000.serial: ttyS3 at MMIO 0x4ae2b000 (irq = 48, base_baud = 3000000) is a 8250

I assume the 48066000.serial: ttyS4 at MMIO 0x48066000  is UART5 based on TI system reference.

So I tried to get signals on P9.11 and P9.13(schematic of BeagleBon AI AM57x page 14 of 19) on Beaglebone AI extension header by the following commands.

 debian@beaglebone:/dev$ echo 12345 > /dev/ttyS4

When I check signal via software scope, I can not get any signal change on the pins. 

Do I need to activate the UART5 ( or /dev/ttyS4 on my dev structure ) before checking? If yes, how can I do to activate it?

Thank you so much!

[ahni...@gmail.com]

want to add pin status

sudo cat   ./debug/pinctrl/4a003400.pinmux/pins

I put mode 4 on *.dts file but the value looks like 0c instead 04. 

...

pin 203 (PIN203) 4a00372c 000c0000 pinctrl-single

pin 204 (PIN204) 4a003730 000c0000 pinctrl-singl

...

And also I used to config-pin and got the following information. I think this config-pin tool is out of date because it showed as uart4 instead of uart5.

do you know if config-pin can be used Beaglebone AI too?

debian@beaglebone:/sys/kernel$ config-pin -l P9.11

default gpio gpio_pu gpio_pd gpio_input uart

debian@beaglebone:/sys/kernel$ config-pin -i P9.11

Pin name: P9_11

Function if no cape loaded: gpio

Function if cape loaded: default gpio gpio_pu gpio_pd gpio_input uart

Function information: gpio0_30 default gpio0_30 gpio0_30 gpio0_30 gpio0_30 uart4_rxd

Kernel GPIO id: 30

PRU GPIO id: 62

debian@beaglebone:/sys/kernel$ config-pin -q P9.11

P9_11 pinmux file not found!

Pin has no cape: P9_11

[ahni...@gmail.com]

I finally found the solution by changing the device tree about uart3 tx. P9.21 uar3 rx P9.22

                                                                      

Verified mode change from 14 to mode 1. it is working as /dev/ttyS2

pin 241 (PIN241) 4a0037c4 00000001 pinctrl-single

pin 240 (PIN240) 4a0037c0 00060001 pinctrl-single

Thanks 

[ahni...@gmail.com]

I would like to share information. 
How to find the map between uart* and ttyS*

Ocp is on-chip peripheral.

 

Uart 3 physical address is 0x4802 0000  (TI manual).

So the mapping address is matched to /tty/ttyS2 (it is actually linked to ttyO2. Please Refer to the below command )

Uart 5 physical address is 0x4806 6000 matched to ttyS4. (it is actually linked to ttyO4. Please Refer to the below command)

 

Etc.

 

I hope it is helpful. 

 

debian@beaglebone:/sys/class/tty$ ls -al | grep ttyS

lrwxrwxrwx  1 root root 0 Mar 12 23:01 ttyS0 -> ../../devices/platform/44000000.ocp/4806a000.serial/tty/ttyS0

lrwxrwxrwx  1 root root 0 Mar 12 23:01 ttyS1 -> ../../devices/platform/44000000.ocp/48422000.serial/tty/ttyS1

lrwxrwxrwx  1 root root 0 Mar 12 23:01 ttyS2 -> ../../devices/platform/44000000.ocp/48020000.serial/tty/ttyS2

lrwxrwxrwx  1 root root 0 Mar 12 23:01 ttyS3 -> ../../devices/platform/44000000.ocp/4ae2b000.serial/tty/ttyS3

lrwxrwxrwx  1 root root 0 Mar 12 23:01 ttyS4 -> ../../devices/platform/4400.ocp/48066000.serial/tty/ttyS4

lrwxrwxrwx  1 root root 0 Mar 12 23:01 ttyS5 -> ../../devices/platform/44000000.ocp/48068000.serial/tty/ttyS5

 

[ahni...@gmail.com]

I hope it is helpful for uart3  /dev/ttyS2 device tree implementation. 

Uart3 RX starts working after the mode update to 

PIN_INPUT_PULLUP | MUX_MODE1 // P9.22b uart3_rxd

Mode is confirmed as the following:

P9.22b   240 fast rx  up   1 uart 2 rxd       serial@48020000 (uart3)

pin 240 (PIN240) 4a0037c0 00060001 pinctrl-single ( instead of 00000001)

UART3 TX was working without any pull up or pull down.

P9_21, MUX_MODE1 ) // P9.21 uart3_txd

pin 241 (PIN241) 4a0037c4 00000001 pinctrl-single

To activate uart3, please add the following code into *.dts file and compile to *.dtb. 

Also please modify the am572*ai.dts file by deactivating the shared pins.

&uart3 {

 status = "okay";

 pinctrl-names = "default";

 pinctrl-0 = <&uart3_pins>;

};

&dra7_pmx_core {

 uart3_pins: uart3 {

  pinctrl-single,pins = <

   DRA7XX_CORE_IOPAD( P9_21, MUX_MODE1 ) // P9.21 uart3_txd

   DRA7XX_CORE_IOPAD( P9_22b, PIN_INPUT_PULLUP | MUX_MODE1) // P9.22b uart3_rxd

   DRA7XX_CORE_IOPAD( P9_22a, MUX_MODE15) // P9.22a driver_off //shared-pin

  >;

 };

 

};

[Jason Kridner]

Thanks for all your shared work. 

The plan for the Fall release (based on GSoC work on-going this summer, if approved, or this might be delayed) is to modify the base device trees and set of overlays to provide at common set of overlays to load for Black/AI. Then, symlinks would be provided that map to UARTs on specific header pins.

See https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec for work-in-progress.

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[ahni...@gmail.com]

Hello Jason,

Thank you for update. 

Could you inform how to use provided dts files  on  https://elinux.org/Beagleboard:BeagleBone_cape_interface_spec ? 

Are their *.dtb files already compiled/copied on /boot/dtbs ?

I used to compile dts file to dtb file and copied it to /boot/dtbs/. 

 

Thank you so much!

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[sharif...@gmail.com]

Hi ahni, Thanks a lot for this info, I will try This out & see if UART3 Works.