>
> Hi guys,
>
> I tried searching for DVI-D to TTL LCD converter and found this
> small one:
>
> http://www.aaeon.com/PD_Products_Detail_AEEE87FC762C45F1AC_F67467B5A6BD44F0B9_30D6012CD30E4BAAAC_US_utf-8.html
> [snip]
>
> Unfortunately (for me) they said they don't have any for 320x240 or
> 480x272 type screens.
Hi Bert,
It appears the Silicon Image DVI deframer/deserialiser/receiver that
they use on those boards only likes working at pixel frequencies
between 25MHz and 165MHz, which limits you to a range of (fairly high)
resolutions.
It also seems that the TFP410 DVI transmitter on the beagleboard has a
similar limitation in that it wants to work at a minimum of 25MHz
pixel clock too, so even if you find a receiver that's able to lock at
very low frequencies you might not get sense out of the beagleboard at
those rates.
(For reference, I'm working from 480x272x50Hz having a pixel clock of
about 6.5MHz and 320x240x50Hz about 3.8MHz.)
I wouldn't feel confident about being able to drive such a small
display from the beagleboard using parallel->DVI->DVI->parallel,
perhaps Gerald/the paid BB hardware guys could advise about the
transmitter.
If you are very good at soldering and willing to take the risk of
ruining your BB it is technically possible to find the LCD data on the
board itself (it is fed from the OMAP3 to the TFP410) and bringing it
out to, say, a TFT panel from a Sony PSP (480x272 ;) ) "should work",
the speeds aren't superhigh at those resolutions. Note you'd have to
buffer the (IIRC 1.8V) outputs up to the (probably) 3.3V input the
display would be expecting. But don't take my advice. =)
Cheers,
Matt
Based on these restrictions, it may still be possible to drive the lower
resolution LCDs. I think there is hardware support in the lcd controller
for pixel doubling. With this, it may be possible to setup a CPLD (small
device like the a 22V10 or smaller) to divide the clocks seen by the LCD
by 2 in X and 2 in Y. Using those figures above, a panel wanting around
6MHz can probally be driven by a 24MHz clock through the DVI processes.
The chain would be something like
OMAP parallel -> DVI -> DVI -> Parallel -> CPLD -> Panel
-- Hunyue
>
>
>
> Cheers,
>
>
>
> Matt
>
>
> >