The only thing I can think of is that you're not enabling the ADC control register. Below is a code snippet from another post.
//Init ADC CTRL register MOV r2, 0x44E0D040 MOV r3, 0x00000005 SBBO r3, r2, 0, 4
From this post: https://groups.google.com/forum/#!msg/beagleboard/0a4tszlq2y0/SQ-Vwyr9A_AJ
The second post. I would not bother replying to that post, but who knows maybe someone would answer ? I doubt it though.
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mov r0, 0x44E004BC
mov r1, 2
sbbo r1, r0, 0, 4
The only thing I can think of is that you're not enabling the ADC control register. Below is a code snippet from another post.
//Init ADC CTRL register MOV r2, 0x44E0D040 MOV r3, 0x00000005 SBBO r3, r2, 0, 4From this post: https://groups.google.com/forum/#!msg/beagleboard/0a4tszlq2y0/SQ-Vwyr9A_AJ
The second post. I would not bother replying to that post, but who knows maybe someone would answer ? I doubt it though.
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(1) I know this because I tried reading the ADC REVISION register using the PRU and got zero as a result.
LDI r2, 0b10 // load clock demand value
MOV r1, 0x44E004BC // load
CM_WKUP_ADC_TSC_CLKCTRL address
SBBO r2, r1
, 0, 1 // write clock register
LDI r5, 0 // clear timeout counter
MOV r3, 0x44E0D000 // load ADC address
AdcWait:
LBBO r0, r3, 0, 4 // load ADC REVISION
QBNE AdcCopy, r0, 0 // if ADC is up -> copy config
ADD r5, r5, 1 // increase timeout counter
QBGE AdcWait, r5.b1, 16 // if no timeout -> wait
AdcCopy:
The PRU hads to access the ADC through the L3_interconnect bus too . . . so the control register for the L3_interconnect must also be enabled.
OTOH, I am still wondering if my kernel isn't the root cause. It seems clear that other people have been able to get ADC control from the PRU, but with 3.8 or 4.1 kernels. I could revert to an older kernel version, but that feels like the wrong approach. I have also been looking at the IIO system, which may be a better approach as it would be more "standard" and portable than using the PRU. (But I *like* using the PRU - it's a nice hammer looking for a nail!)
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The only device tree overlay I needed is what I have below; no need to load the BB-ADC overlay.
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PRU Code
//--------------------------------------------------------------------
// Enable and/or turn on hardware
// Code in this section must be ordered as listed for proper
// hardware startup.
// Enable OCP
lbco r0, PRU_ICSS_CFG_base, PRU_CFG_SYSCFG, 4
clr r0, 4
sbco r0, PRU_ICSS_CFG_base, PRU_CFG_SYSCFG, 4
// Enable ADC clock, wait for ADC module to start before proceeding
mov r0, CM_WKUP_base + CM_WKUP_ADC_TSC_CLKCTRL
mov r1, 2
sbbo r1, r0, 0, 4
mov r1, 0 // clear timeout counter
AdcWait:
LBBO r0, adc_base, ADC_REVISION, 4 // load ADC REVISION
QBNE AdcUp, r0, 0 // exit if ADC is running
ADD r1, r1, 1 // increase timeout counter
QBGE AdcWait, r1.b1, 16 // if no timeout -> wait
AdcUp:
//--------------------------------------------------------------------
...
QBGE AdcWait, r1.b1, 16 // if no timeout -> wait
SBCO r1, DRam, 0, 4 // store timeout counter in DRam
HALT // stop PRU, since ADC isn't ready
AdcUp:
...
A question though: Under what circumstances would the ADC not start?
I am facing some issues in the project you suggested : https://github.com/ehayon/BeagleBone-GPIO/blob/master/src/gpio.c