Why is the SPI0 clock output configured as an input???

[Jon Turner]

The overlay for the SPI0 interface includes the following lines

         pinctrl-single,pins = <  
          0x150 0x30 /* spi0_sclk, INPUT_PULLUP | MODE0 */  
          0x154 0x30 /* spi0_d0, INPUT_PULLUP | MODE0 */  
          0x158 0x10 /* spi0_d1, OUTPUT_PULLUP | MODE0 */  
          0x15c 0x10 /* spi0_cs0, OUTPUT_PULLUP | MODE0 */  
         >;  

Notice the first line, which specifies that the spi0 clock signal is an input with a pullup enabled.

This does not make sense to me, since every diagram I have seen (for example in Derek Molloy's

book, Exploring Beaglebone) shows the clock signal as an output from the BeagleBone. I have checked

the BeagleBone schematic and the processor pin for this signal connects only to the P9 header.

So the only way it would make sense for this pin to be an input is if the user is expected to have

a clock generation circuit on the cape. It's hard for me to imagine that this is the intended usage.

I have seen this same configuration for the overlay in multiple places, so I am guessing it is

correct, but I cannot understand why. Can someone knowledgable out there please enlighten me?

Thanks,

Jon Turner

[John Syne]

The pin direction is only relevant for GPIO. For subsystems like SPI, the pin direction is defined by the subsystem, not the pin direction. 

Regards,

John

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[John Syne]

The pin direction is only relevant for GPIO. For subsystems like SPI, the pin direction is defined by the subsystem, not the pin direction defined by pinctrl-single.

Regards,

John

On Mar 7, 2017, at 2:40 PM, Jon Turner <jontu...@gmail.com> wrote:

[Jon Turner]

The pin direction is only relevant for GPIO. For subsystems like SPI, the pin direction is defined by the subsystem, not the pin direction defined by pinctrl-single.

Regards,

John

Hmm, ok. So do the configuration bits have some other interpretation when the pin is not configured

as a gpio? If so, where is this documented? 

Jon 

[John Syne]

Look at Chapter 9 in the AM3358 Technical Reference Manual. The section on RX Active says:

"9.2.2.3 RX Active

The RXACTIVE bit is used to enable and disable the input buffer. This control can be used to help with power leakage or device isolation through the I/O. The characteristic of the signal is ultimately dictated by the mux mode the pad is put into.”

Regards,

John

Jon 

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