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Daniel Gorsulowski
Dec 16, 2016, 2:50:19 AM12/16/16
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Hi!
I have an issue with a custom board, based on BeagleBone Black (BEAGLEBK) and AM3359 ICS (TMDSICE3359) design.
This board has 3 Ethernet Ports:
Port1: on CPSW MII1 with PHY
address 0 --> eth0
Port2: on PRU0 with PHY address 1 -->
eth1
Port3: on PRU1 with PHY address 0 --> eth2
According to http://processors.wiki.ti.com/index.php/PRU-ICSS_Ethernet I'm going to utilize all 3 ports on linux.
Following basics seems to work:
The PRU-ICSS firmware binaries are loaded:
[ 1.608087] remoteproc0: 4a334000.pru0 is available
[ 1.612060] remoteproc0: Note: remoteproc is still under development and considered experimental.
[ 1.620117] remoteproc0: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.
[ 1.629876] pru-rproc 4a334000.pru0: booting the PRU core manually
[ 1.635040] remoteproc0: powering up 4a334000.pru0
[ 1.638822] remoteproc0: Booting fw image am335x-pru0-fw, size 3893
[ 1.644269] ti-pruss 4a300000.pruss: configured system_events = 0x0000060000500000 intr_channels = 0x00000095 host_intr = 0x00000115
[ 1.655418] remoteproc0: remote processor 4a334000.pru0 is now up
[ 1.660562] pru-rproc 4a334000.pru0: PRU rproc node /ocp/pruss@4a300000/pru0@4a334000 probed successfully
[ 1.669745] remoteproc1: 4a338000.pru1 is available
[ 1.673642] remoteproc1: Note: remoteproc is still under development and considered experimental.
[ 1.681692] remoteproc1: THE BINARY FORMAT IS NOT YET FINALIZED, and backward compatibility isn't yet guaranteed.
[ 1.691380] pru-rproc 4a338000.pru1: booting the PRU core manually
[ 1.696534] remoteproc1: powering up 4a338000.pru1
[ 1.700315] remoteproc1: Booting fw image am335x-pru1-fw, size 3893
[ 1.705741] ti-pruss 4a300000.pruss: configured system_events = 0x0060000000a00000 intr_channels = 0x0000012a host_intr = 0x0000022a
[ 1.716890] remoteproc1: remote processor 4a338000.pru1 is now up
[ 1.722036] pru-rproc 4a338000.pru1: PRU rproc node /ocp/pruss@4a300000/pru1@4a338000 probed successfullyThe Linux kernel networking driver is loaded:
[ 4.265812] prueth pruss_eth: port 1: using random MAC addr: 8e:ff:9e:49:09:50
[ 4.345300] prueth pruss_eth: port 2: using random MAC addr: 1e:b4:fc:c4:f3:6a
[ 4.428260] prueth pruss_eth: TI PRU ethernet driver initializedafter executing "ifup eth1" connecting and disconnecting Port2 is recognized, "eth1: Link is Up - 100Mbps/Full - flow control off" resp. "eth1: Link is Down" is printed
So MDIO interface seems to work too
Additional network related boot infos:
[ 1.385099] libphy: Fixed MDIO Bus: probed
[ 1.439545] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6
[ 1.444628] davinci_mdio 4a101000.mdio: detected phy mask fffffffe
[ 1.451088] libphy: 4a101000.mdio: probed
[ 1.454086] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver unknown
[ 1.462229] cpsw 4a100000.ethernet: No slave[1] phy_id, phy-handle, or fixed-link property
[ 1.469734] cpsw 4a100000.ethernet: Detected MACID = 00:02:27:00:0d:09
[ 1.526565] ti-pruss 4a300000.pruss: creating PRU cores and other child platform devices
[ 1.535277] irq: no irq domain found for /ocp/pruss@4a300000/intc@4a320000 !
[ 1.542073] irq: no irq domain found for /ocp/pruss@4a300000/intc@4a320000 !
[ 1.581511] davinci_mdio 4a332400.mdio: davinci mdio revision 1.6
[ 1.586583] libphy: 4a332400.mdio: probed
[ 1.591594] davinci_mdio 4a332400.mdio: phy[0]: device 4a332400.mdio:00, driver unknown
[ 1.598723] davinci_mdio 4a332400.mdio: phy[1]: device 4a332400.mdio:01, driver unknown
[ 8.611871] net eth0: initializing cpsw version 1.12 (0)
[ 8.616188] net eth0: initialized cpsw ale version 1.4
[ 8.620249] net eth0: ALE Table size 1024
[ 8.678873] net eth0: phy found : id is : 0x221560
[ 8.682667] libphy: PHY not found
[ 8.684914] net eth0: phy "" not found on slave 1, err -19
[ 11.684281] cpsw 4a100000.ethernet eth0: Link is Up - 100Mbps/Full - flow control off
[ 33.201398] net eth1: started <-- after "ifup eth1"
[ 34.406170] eth1: Link is Up - 100Mbps/Full - flow control off
Problems:
MII interface doesn't work, there is no network traffic at all
Releasing PHY reset doesn't work, so I had to implement a workaround (see device tree below)
PHY on Port3 stays in reserved factory mode (known hardware issue, I'm working on it)
My device tree (issue related extracts):
#include "am33xx.dtsi"
/ {
...
aliases {
ethernet0 = &cpsw_emac0;
ethernet1 = &pruss_emac0;
ethernet2 = &pruss_emac1;
};
...
/* Dual mac ethernet application node on icss */
pruss_eth {
compatible = "ti,am3359-prueth";
pruss = <&pruss>;
sram = <&ocmcram_nocache>;
interrupt-parent = <&pruss_intc>;
pinctrl-0 = <&pruss_eth_default>;
pinctrl-names = "default";
pruss_emac0: ethernet-mii0 {
phy-handle = <&pruss_eth0_phy>;
phy-mode = "mii";
interrupts = <20>, <22>;
interrupt-names = "rx", "tx";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
pruss_emac1: ethernet-mii1 {
phy-handle = <&pruss_eth1_phy>;
phy-mode = "mii";
interrupts = <21>, <23>;
interrupt-names = "rx", "tx";
/* Filled in by bootloader */
local-mac-address = [00 00 00 00 00 00];
};
};
};
...
&gpio2 {
pinctrl-names = "default";
pinctrl-0 = <&gpio2_pins>;
status = "okay";
ti,no-reset-on-init;
p12 {
gpios = <12 GPIO_ACTIVE_HIGH>; // I had to define this here, see PHY-reset issue
output-high;
line-name = "RST_PRUPHY#";
};
};
...
&am33xx_pinmux {
...
gpio2_pins: gpio2_pins {
pinctrl-single,pins = <
0xb8 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* (T3) lcd_data6.gpio2[12], RST_PRUPHY# */ // I had to define this here, see PHY-reset issue
>;
};
...
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
0x108 (PIN_INPUT_PULLUP | MUX_MODE0) /* (H16) gmii1_col.gmii1_col */
0x10c (PIN_INPUT_PULLUP | MUX_MODE0) /* (H17) gmii1_crs.gmii1_crs */
0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
>;
};
cpsw_sleep: cpsw_sleep {
pinctrl-single,pins = <
/* Slave 1 reset value */
0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
davinci_mdio_default: davinci_mdio_default {
pinctrl-single,pins = <
/* MDIO */
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* (M17) mdio_data.mdio_data */
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* (M18) mdio_clk.mdio_clk */
>;
};
davinci_mdio_sleep: davinci_mdio_sleep {
pinctrl-single,pins = <
/* MDIO reset value */
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
>;
};
...
pruss_eth_default: pruss_eth_default {
pinctrl-single,pins = <
//PRUETH0
0xa0 (PIN_INPUT | MUX_MODE2) /* (R1) lcd_data0.pr1_mii_mt0_clk */
0xb4 (PIN_OUTPUT | MUX_MODE2) /* (T2) lcd_data5.pr1_mii0_txd0 */
0xb0 (PIN_OUTPUT | MUX_MODE2) /* (T1) lcd_data4.pr1_mii0_txd1 */
0xac (PIN_OUTPUT | MUX_MODE2) /* (R4) lcd_data3.pr1_mii0_txd2 */
0xa8 (PIN_OUTPUT | MUX_MODE2) /* (R3) lcd_data2.pr1_mii0_txd3 */
0xcc (PIN_INPUT | MUX_MODE5) /* (U4) lcd_data11.pr1_mii0_rxd0 */
0xc8 (PIN_INPUT | MUX_MODE5) /* (U3) lcd_data10.pr1_mii0_rxd1 */
0xc4 (PIN_INPUT | MUX_MODE5) /* (U2) lcd_data9.pr1_mii0_rxd2 */
0xc0 (PIN_INPUT | MUX_MODE5) /* (U1) lcd_data8.pr1_mii0_rxd3 */
0xa4 (PIN_OUTPUT | MUX_MODE2) /* (R2) lcd_data1.pr1_mii0_txen */
0xd8 (PIN_INPUT | MUX_MODE5) /* (V4) lcd_data14.pr1_mii_mr0_clk */
0xdc (PIN_INPUT | MUX_MODE5) /* (T5) lcd_data15.pr1_mii0_rxdv */
0xd4 (PIN_INPUT | MUX_MODE5) /* (V3) lcd_data13.pr1_mii0_rxer */
0xd0 (PIN_INPUT | MUX_MODE5) /* (V2) lcd_data12.pr1_mii0_rxlink */
// PRUETH1
0x40 (PIN_INPUT | MUX_MODE5) /* (R13) gpmc_a0.pr1_mii_mt1_clk */
0x50 (PIN_OUTPUT | MUX_MODE5) /* (R14) gpmc_a4.pr1_mii1_txd0 */
0x4c (PIN_OUTPUT | MUX_MODE5) /* (T14) gpmc_a3.pr1_mii1_txd1 */
0x48 (PIN_OUTPUT | MUX_MODE5) /* (U14) gpmc_a2.pr1_mii1_txd2 */
0x44 (PIN_OUTPUT | MUX_MODE5) /* (V14) gpmc_a1.pr1_mii1_txd3 */
0x60 (PIN_INPUT | MUX_MODE5) /* (V16) gpmc_a8.pr1_mii1_rxd0 */
0x5c (PIN_INPUT | MUX_MODE5) /* (T15) gpmc_a7.pr1_mii1_rxd1 */
0x58 (PIN_INPUT | MUX_MODE5) /* (U15) gpmc_a6.pr1_mii1_rxd2 */
0x54 (PIN_INPUT | MUX_MODE5) /* (V15) gpmc_a5.pr1_mii1_rxd3 */
0x74 (PIN_OUTPUT | MUX_MODE5) /* (U17) gpmc_wpn.pr1_mii1_txen */
0x64 (PIN_INPUT | MUX_MODE5) /* (U16) gpmc_a9.pr1_mii_mr1_clk */
0x68 (PIN_INPUT | MUX_MODE5) /* (T16) gpmc_a10.pr1_mii1_rxdv */
0x6c (PIN_INPUT | MUX_MODE5) /* (V17) gpmc_a11.pr1_mii1_rxer */
0x78 (PIN_INPUT | MUX_MODE5) /* (U18) gpmc_be1n.pr1_mii1_rxlink */
>;
};
pruss_mdio_default: pruss_mdio_default {
pinctrl-single,pins = <
0x8c (PIN_OUTPUT_PULLUP | MUX_MODE5) /* (V12) gpmc_clk.pr1_mdio_mdclk */
0x88 (PIN_INPUT_PULLUP | MUX_MODE5) /* (T13) gpmc_csn3.pr1_mdio_data */
//0xb8 (PIN_INPUT_PULLUP | MUX_MODE7) /* (T3) lcd_data6.gpio2[12], RST_PRUPHY# */ // I had to disable this here, see PHY-reset issue
>;
};
};
...
&pruss_mdio {
pinctrl-0 = <&pruss_mdio_default>;
pinctrl-names = "default";
//reset-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; // I had to disable this here, see PHY-reset issue
//reset-delay-us = <2>; /* PHY datasheet states 1uS min */
status = "okay";
pruss_eth0_phy: ethernet-phy@0 {
reg = <0>;
};
pruss_eth1_phy: ethernet-phy@1 {
reg = <1>;
};
};
&cpsw_emac0 {
phy_id = <&davinci_mdio>, <0>;
phy-mode = "mii";
};
&cpsw_emac1 {
status = "disabled";
};
&mac {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&cpsw_default>;
pinctrl-1 = <&cpsw_sleep>;
status = "okay";
};
&davinci_mdio {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&davinci_mdio_default>;
pinctrl-1 = <&davinci_mdio_sleep>;
status = "okay";
};
...
I guess, something is wrong with my device tree - but what?
Yiling Cao
Dec 17, 2016, 9:34:29 PM12/17/16
to beagl...@googlegroups.com
Hi, are the power sequence /reset timing on the 3 ports correct?
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Daniel Gorsulowski
Dec 19, 2016, 2:49:21 AM12/19/16
to BeagleBoard
Hi!
Are you talking about the PHYs?
The normal way should be (as far as I understand) to cede the reset-timing to the prueth driver. But if I do so (define reset-gpios and reset-delay-us in pruss-mdio node), the PHY reset is never released.
So I handle the PHY-reset manually via GPIO access within a script. (The same script works fine if I use the PRU ports with EtherCAT or ProfiNet firmware)
Btw. the CPSW ethernet port (eth0) works fine, if I didn't mention it clearly enough.
Are you talking about the PHYs?
The normal way should be (as far as I understand) to cede the reset-timing to the prueth driver. But if I do so (define reset-gpios and reset-delay-us in pruss-mdio node), the PHY reset is never released.
So I handle the PHY-reset manually via GPIO access within a script. (The same script works fine if I use the PRU ports with EtherCAT or ProfiNet firmware)
Btw. the CPSW ethernet port (eth0) works fine, if I didn't mention it clearly enough.
Am Sonntag, 18. Dezember 2016 03:34:29 UTC+1 schrieb c2h2:
Hi, are the power sequence /reset timing on the 3 ports correct?
On Fri, Dec 16, 2016 at 3:50 PM, Daniel Gorsulowski <daniel.go...@gmail.com> wrote:
Hi!
I have an issue with a custom board, based on BeagleBone Black (BEAGLEBK) and AM3359 ICS (TMDSICE3359) design.
...
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