It will be impossible to do that with that amount of channels. Each
sample has 16 bit.
48 Channels * 450 kS/s * 16 bit = 345.6 Mbit/S.
Besides that is probably beyond any bus speed on the SoC. It would as
well require you to interface with 24 SPI lines in parallel in full
speed. There is absolutely no way to do that on a BeagleBone. You'll
have to go for a FPGA or a faster ADC with analog multiplexing in you
front-end.
Bests,
Julian
On Tue, Sep 22, 2015 at 6:10 PM, Antônio Albuquerque <
atd...@gmail.com> wrote:
> something around 450kS/s