> Just checked the code - Seems like both x-loader and U-boot uses 1-bit mode:
>
> See cpu/omap3/mmc.c for x-loader (search for HCTL)
> See drivers/mmc/omap3_mmc.c for u-boot (search for hctl)
Thanks much Soren. Indeed, I finally scoped out D0-D3 and confirmed
that only D0 is active during U-Boot loading, and kernel loading. D1-
D3 become active after the SD/MMC interface is registered and brought
up by the kernel, so it looks like there is a hardware issue. It
looks like the bit-timing for 1-bit mode is around 90 nS per bit, or
~11 MHz. I haven't been able to successfully capture the speed of the
bus when it goes to 4-bit mode since it is only there for a very brief
period before it bombs out (and I don't have an adequate trigger
yet...may just wiggle an i/o line right before the interface comes up
to trigger my scope). I'm not ruling out a speed issue either...could
be the 4-bit mode runs at a faster bit rate than 1-bit mode, which
causes the issues. More playing shortly...
>
> Can you make your board do a ROM code boot directly from MMC? (ROM-code
> reading MLO from MMC?)
> IFAIR the ROM-code will try to switch to 4-bit-mode, which should give you
> the error at this time in case your theory is right :-)
Good idea. Alternately, I was going to see if I could force the
kernel to stick with 1-bit mode instead of 4-bit mode, which would
hopefully yield a working system (albeit slower).
>
> Another thing to try would be to try to lower the MMC clock in the Linux
> Kernel and/or cool/heat the card to see if it changes anything...
>
> Good luck - Happy debugging
Again, much appreciated for the quick response and insight.
Regards,
John