BBAI cape EEPROM pin usage section

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Diane Miller

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Sep 8, 2020, 6:19:26 PM9/8/20
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Where can I find the format of the cape EEPROM pin usage section for the BeagleBone AI? I need to know the ordering of the pins as well as the format of each pin's 16-bit field.

From what I could figure out on my own the BBB pins are in GPIO order, with the non-muxed AINx pins at the end of the table. Can anyone confirm that this same ordering applies to the BBAI? How are the a/b pins handled (such as 9.19a/b)?

It seems that the BBAI pin bitfield's format must differ from the BBB since the AM572x has a 4-bit muxmode field, whereas the AM335x has only 3 bits. Has the BBAI's EEPROM format been posted anywhere?

Thanks,
Diane

Robert Nelson

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Sep 8, 2020, 6:23:52 PM9/8/20
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This feature of the spec was never utilized.



Regards

Diane Miller

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Sep 9, 2020, 8:32:32 AM9/9/20
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Are there any plans to implement this in the future? If not, is the device tree the only way to set up the pin muxing? 

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Jason Kridner

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Sep 9, 2020, 9:34:25 AM9/9/20
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On Wed, Sep 9, 2020 at 8:11 AM Diane Miller <diane.e...@gmail.com> wrote:
Are there any plans to implement this in the future?

No.
 
If not, is the device tree the only way to set up the pin muxing? 

U-boot sets up the device tree and initial pin mux. Using the device tree configured by u-boot is the simplest way to set the pinmux, but you can also change the default pin muxing in u-boot outside of the device tree--just make sure the kernel doesn't change it by having a device tree that doesn't match.
 
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Diane Miller

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Sep 9, 2020, 3:43:45 PM9/9/20
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Thanks very much for your quick responses, Jason and Robert, I appreciate the assistance. 

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