Can MikroElektronika eth click work with BBB

[johan...@orica.com]

Hello

I'm trying to get the eth click board from MikroElektronika to work on a BBB but I fail. I can see that others successfully have used it on a PocketBeagle but I'm running on a BBB industrial.

To fit the board I use the mikroBUS cape and I use slot 1 on the cape.

The Debian image from 2018-03-05 is used.

The file /boot/uEnv.txt has been modified with:

enable_uboot_overlays=1

###

###Overide capes with eeprom

uboot_overlay_addr0=/lib/firmware/BB-mBUS_1_eth_click-00A0.dtbo

#uboot_overlay_addr1=/lib/firmware/<file1>.dtbo

#uboot_overlay_addr2=/lib/firmware/<file2>.dtbo

#uboot_overlay_addr3=/lib/firmware/<file3>.dtbo

###Cape Universal Enable

#enable_uboot_cape_universal=1

I have modified the file PB-SPI0-ETH-CLICK.dts to adapt to correct signals (if it's correct I don't know for sure)

this is later compiled with make BB-mBUS_1_eth_click.dtbo

/*

 * Copyright (C) 2017 Robert Nelson <robertcnelson>

 * 

 * Modified by Johan Lind for mikroBUS cape slot 1     (eth click)

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

/dts-v1/;

/plugin/;

#include <dt-bindings/board/am335x-bbw-bbb-base.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/pinctrl/am33xx.h>

#include <dt-bindings/interrupt-controller/irq.h>

/ {

fragment@0 {

target = <&am33xx_pinmux>;

__overlay__ {

enc28j60_pins: pinmux_enc28j60_pins {

pinctrl-single,pins = <

AM33XX_IOPAD(0x0840, PIN_INPUT | MUX_MODE7 ) /* gpio1[16] INT    P9.15 */

AM33XX_IOPAD(0x0878, PIN_INPUT | MUX_MODE7 ) /* gpio1[28] RESET  P9.12 */

>;

};

pb_spi1_pins: pinmux_pb_spi1_pins {

pinctrl-single,pins = <

AM33XX_IOPAD(0x0990, PIN_INPUT | MUX_MODE3 ) /* spi1_sclk P9.31 */

AM33XX_IOPAD(0x0994, PIN_INPUT | MUX_MODE3 ) /* spi1_d0   P9.29*/

AM33XX_IOPAD(0x0998, PIN_INPUT | MUX_MODE3 ) /* spi1_d1   P9.30*/

AM33XX_IOPAD(0x099c, PIN_INPUT | MUX_MODE3 ) /* spi1_cs0  P9.28*/

>;

};

};

};

fragment@1 {

target = <&ocp>;

__overlay__ {

P9_15_pinmux {       

status = "disabled";

};

P9_12_pinmux {       

status = "disabled";

};

P9_31_pinmux {       

status = "disabled";

};

P9_29_pinmux {      

status = "disabled";

};

P9_30_pinmux {     

status = "disabled";

};

P9_28_pinmux {

status = "disabled";

};

};

};

fragment@2 {

target = <&spi1>;

__overlay__ {

status = "okay";

pinctrl-names = "default";

pinctrl-0 = <&pb_spi1_pins>;

#address-cells = <1>;

#size-cells = <0>;

channel@0 {

status = "disabled";

};

channel@1 {

status = "disabled";

};

enc28j60: ethernet@1 {

compatible = "microchip,enc28j60";

pinctrl-names = "default";

pinctrl-0 = <&enc28j60_pins>;

reg = <0x1>;

interrupt-parent = <&gpio1>;                 /* P9.15 gpio1[16] */

interrupts = <16 IRQ_TYPE_EDGE_FALLING>;     /* P9.15 gpio1[16] */

spi-max-frequency = <16000000>;

};

};

};

};

Looking at this it looks like the pins are configured for SPI usage.

$ sudo cat /sys/kernel/debug/pinctrl/44e10800.pinmux/pinmux-pins | grep spi

pin 100 (PIN100): 481a0000.spi (GPIO UNCLAIMED) function pinmux_pb_spi1_pins group pinmux_pb_spi1_pins

pin 101 (PIN101): 481a0000.spi (GPIO UNCLAIMED) function pinmux_pb_spi1_pins group pinmux_pb_spi1_pins

pin 102 (PIN102): 481a0000.spi (GPIO UNCLAIMED) function pinmux_pb_spi1_pins group pinmux_pb_spi1_pins

pin 103 (PIN103): 481a0000.spi (GPIO UNCLAIMED) function pinmux_pb_spi1_pins group pinmux_pb_spi1_pins

However the version command give

$ sudo /opt/scripts/tools/version.sh

git:/opt/scripts/:[e307a944e0be0610ff5296e0abe4ad31a6e70daa]

eeprom:[A335BNLTEIA04816BBBK24A9]

model:[TI_AM335x_BeagleBone_Black]

dogtag:[BeagleBoard.org Debian Image 2018-03-05]

bootloader:[eMMC-(default)]:[/dev/mmcblk1]:[U-Boot 2018.01-00002-ge9ff418fb8]:[location: dd MBR]

kernel:[4.9.82-ti-r102]

nodejs:[v6.13.0]

uboot_overlay_options:[enable_uboot_overlays=1]

uboot_overlay_options:[uboot_overlay_addr0=/lib/firmware/BB-mBUS_1_eth_click-00A0.dtbo]

pkg:[bb-cape-overlays]:[4.4.20180625.0-0rcnee0~stretch+20180625]

pkg:[bb-wl18xx-firmware]:[1.20170829-0rcnee2~stretch+20180104]

pkg:[firmware-ti-connectivity]:[20170823-1rcnee0~stretch+20170830]

groups:[debian : debian adm kmem dialout cdrom floppy audio dip video plugdev users systemd-journal i2c bluetooth netdev cloud9ide gpio pwm eqep admin spi tisdk weston-launch xenomai]

cmdline:[console=ttyO0,115200n8 bone_capemgr.uboot_capemgr_enabled=1 root=/dev/mmcblk1p1 ro rootfstype=ext4 rootwait coherent_pool=1M net.ifnames=0 quiet]

dmesg | grep pinctrl-single

[    1.393378] pinctrl-single 44e10800.pinmux: 142 pins at pa f9e10800 size 568

[    1.640904] pinctrl-single 44e10800.pinmux: pin PIN103 already requested by 481a0000.spi; cannot claim for 48038000.mcasp

[    1.652180] pinctrl-single 44e10800.pinmux: pin-103 (48038000.mcasp) status -22

[    1.659672] pinctrl-single 44e10800.pinmux: could not request pin 103 (PIN103) from group mcasp0_pins  on device pinctrl-single

dmesg | grep gpio-of-helper

[    1.394409] gpio-of-helper ocp:cape-universal: ready

END

debian@beaglebone:~$

This indicates there is a conflict over the used pins.

My questions are:

1) Where is mcasp0_pins configured?

2) Can I remove the use of mcasp0_pins?

3) What does mcasp0_pins do?

4) How do I verify if overlay was loaded (I assume that the line in version.sh only show that it tried to load)?

5) Anything else you can say to point me in the right direction (errors in dts file, missing commands, etc)?

[Johan Lind]

I have done some more trials to get this working , but still no luck.

I have written a new device tree file BB-mBUS_3_eth_click-00A0.dts, listed in the end of this post. This time I wrote it for slot 3 on the cape.

This slot use the other SPI port (spi0 instead of spi1 that is on slots 1,2,4).

My new questions are:

1) Do I have to do anything else than modifying the file /boot/uEnv.txt once the dts/dtbo file is correct to get a "eth click" board working?

2) Can anyone tell me if I'm doing the interrupt configuration correct in the attached source file? (I don't know the syntax for this)

3) Anything else that is wrong anyone can point out?

/*

 * Copyright (C) 2017 Robert Nelson <robertcnelson>

 * 

 * Modified by Johan Lind for mikroBUS cape slot 3     (eth click)

 * Note that to use SPI in slot 3 jumpers J7/J8 on cape must be

 * configured for SPI usage.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 */

/dts-v1/;

/plugin/;

#include <dt-bindings/board/am335x-bbw-bbb-base.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/pinctrl/am33xx.h>

#include <dt-bindings/interrupt-controller/irq.h>

/ {

fragment@0 {

target = <&am33xx_pinmux>;

__overlay__ {

enc28j60_pins: pinmux_enc28j60_pins {

pinctrl-single,pins = <

AM33XX_IOPAD(0x088c, PIN_INPUT | MUX_MODE7 ) /* gpio2[1]  INT    P8.18 */

AM33XX_IOPAD(0x0828, PIN_INPUT | MUX_MODE7 ) /* gpio0[26] RESET  P8.14 */

>;

};

bb_spi0_pins: pinmux_bb_spi0_pins {

pinctrl-single,pins = <

AM33XX_IOPAD(0x0950, PIN_INPUT | MUX_MODE0 ) /* spi0_sclk P9.22 */

AM33XX_IOPAD(0x0954, PIN_INPUT | MUX_MODE0 ) /* spi0_d0   P9.21*/

AM33XX_IOPAD(0x0958, PIN_INPUT | MUX_MODE0 ) /* spi0_d1   P9.18*/

AM33XX_IOPAD(0x095c, PIN_INPUT | MUX_MODE0 ) /* spi0_cs0  P9.17*/

>;

};

};

};

fragment@1 {

target = <&ocp>;

__overlay__ {

P8_18_pinmux {       

status = "disabled";

};

P8_14_pinmux {       

status = "disabled";

};

P9_22_pinmux {       

status = "disabled";

};

P9_21_pinmux {      

status = "disabled";

};

P9_18_pinmux {     

status = "disabled";

};

P9_17_pinmux {

status = "disabled";

};

};

};

fragment@2 {

target = <&spi1>;

__overlay__ {

status = "okay";

pinctrl-names = "default";

pinctrl-0 = <&bb_spi0_pins>;

#address-cells = <1>;

#size-cells = <0>;

channel@0 {

status = "disabled";

};

channel@1 {

status = "disabled";

};

enc28j60: ethernet@1 {

compatible = "microchip,enc28j60";

pinctrl-names = "default";

pinctrl-0 = <&enc28j60_pins>;

reg = <0x1>;

interrupt-parent = <&gpio2>;                 /* P8.18 gpio2[1] */

interrupts = <1 IRQ_TYPE_EDGE_FALLING>;     /* P8.18 gpio2[1] */

spi-max-frequency = <16000000>;

};

};

};

};

[Johan Lind]

OK, I'm making progress.

By modifying the dts file (mostly trial and error) I now have something that works even if there are still issues.

Just like in another post there is a 90s delay during boot. Also the original eth0 (on BBB) is renamed to rename3.

Anyone got any ideas on what's going on there?

Here is the dts that got me this far. If I get the slot 1 version to work I will post that too.

target = <&spi0>;

__overlay__ {

status = "okay";

pinctrl-names = "default";

pinctrl-0 = <&bb_spi0_pins>;

#address-cells = <1>;

#size-cells = <0>;

channel@0 {

status = "disabled";

};

channel@1 {

status = "disabled";

};

enc28j60: ethernet@1 {

compatible = "microchip,enc28j60";

pinctrl-names = "default";

pinctrl-0 = <&enc28j60_pins>;

reg = <0x0>;

[Robert Nelson]

You might need to add an alises:

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm/boot/dts/am33xx.dtsi?h=v4.18-rc2#n22

ethernet2 = &enc28j60;

Regards,

--
Robert Nelson
https://rcn-ee.com/

[Robert Nelson]

Okay, this took a few more hacks..

Disable:

/etc/udev/rules.d/70-persistent-net.rules

Remove the net option from /boot/uEnv.txt

Then got it working..

https://github.com/beagleboard/bb.org-overlays/blob/master/src/arm/BB-mBC1-ETH-CLICK.dts

I'll work on adding it to 2/3/4 with full pin doc's so we can easily
port more clicks..

[Robert Nelson]

On Wed, Jun 27, 2018 at 5:23 PM, Robert Nelson <robert...@gmail.com> wrote:
> Okay, this took a few more hacks..
>
> Disable:
>
> /etc/udev/rules.d/70-persistent-net.rules
>
> Remove the net option from /boot/uEnv.txt
>
> Then got it working..
>
> https://github.com/beagleboard/bb.org-overlays/blob/master/src/arm/BB-mBC1-ETH-CLICK.dts
>
> I'll work on adding it to 2/3/4 with full pin doc's so we can easily
> port more clicks..

and this was on v4.18-rc2..

[Johan Lind]

Thank you very much Robert!

Here are my results testing with your new overlay and configuration changes:

I tried it first on my board with the image Debian 9.3 2018-03-05 but it did not work.

Then I tried Debian Buster 2018-06-17 and it worked.

Next I selected the image that I will continue with, Debian 9.4 2018-06-17. It worked on that too.

I'm not sure about what net option you suggested to remove from /boot/uEnv.txt 

I tried with this change:

cmdline=coherent_pool=1M quiet

#cmdline=coherent_pool=1M net.ifnames=0 quiet

both worked, however boot time was 10s faster with the original line.

The removal of data in /etc/udev/rules.d/70-persistent-net.rules was needed.

[Robert Nelson]

On Thu, Jun 28, 2018 at 6:48 AM, Johan Lind <johan...@orica.com> wrote:
> Thank you very much Robert!
>
> Here are my results testing with your new overlay and configuration changes:
> I tried it first on my board with the image Debian 9.3 2018-03-05 but it did
> not work.
> Then I tried Debian Buster 2018-06-17 and it worked.
> Next I selected the image that I will continue with, Debian 9.4 2018-06-17.
> It worked on that too.

There was some kernel backports to support the ETH device, just make
sure you have the latest kernel and u-boot overlays enabled..

> I'm not sure about what net option you suggested to remove from
> /boot/uEnv.txt
> I tried with this change:
> cmdline=coherent_pool=1M quiet
> #cmdline=coherent_pool=1M net.ifnames=0 quiet
> both worked, however boot time was 10s faster with the original line.
>
> The removal of data in /etc/udev/rules.d/70-persistent-net.rules was needed.

So far it looks like removing
/etc/udev/rules.d/70-persistent-net.rules is enough..

Kinda went crazy this afternoon, added ETH & ETH-WIZ support to spots 2, 3, 4.

You can install both ETH & ETH-WIZ into any location. (i only have one
of each, so couldn't test more..)

Slot 1,2,4: share one spi bus..
Slot 3: SPI: make sure to unsolder/solder J7/J8 on back, it's also the
only slot with it's own spi bus.. (You'll lose TX/RX on Slot 1)
Slot 4: This has a non-hardware CS pin (gpio-cs), thus no DMA avaiable.