Ok...
A bit more research and I have found that DMTIMER2 is running. I must have typed int he wrong address the first time I checked.
As with all things memory map, the control of this timer is a bit cryptic, but is looks as though the TCRR which is to say the actual incrementing register is available at 0x4804003C.
It looks like DMTIMER1 is sort of a wierd 1 of clock, and that DMTIMER 3-7 are not running at all... interestingly devmem2 generates a buss error when I try to read their registers. I'm not sure why that would happen?
It seems that the rate that DMTIMER2 is incrementing is actually controlled from CLKSEL_TIMER2_CLK which is in the CM_DPLL register bank with is located at 0x44E00500 with an offset of 8.
This indicates that DMTIMER2 is being fed by the "system clock". Oddly according to my testing, it appears that this "system clock" is not actually a 1Ghz clock, but rather a 25Mhz clock.