Skip to first unread message
Dean Claxton
Apr 11, 2017, 2:00:53 AM4/11/17
to BeagleBoard
Hi,
I'm building a custom cape that uses a number of on-chip peripherals including UART1,2,4,5, SPI1, I2C1, I2C2 (cape eeprom), ADC, plus a number of GPIO.
At the moment I'm in the process of testing the first hardware revision of the cape, and creating the driver overlay - I'd like to be able to include everything in the one overlay.
So far most things are working but I do have a couple of issues. For some reason only RX is working on UART1 and UART2 - UART4 and 5 are working properly for both RX and TX.
Is there something I am missing with UART1 and 2 in regard to TX? The guts of my overlay is shown below :
exclusive-use =
/* the pin header uses */
"P8.7", /* gpio2_2 GPIO1 */
"P8.8", /* gpio2_3 5V_LOAD1_EN */
"P8.9", /* gpio2_5 GPIO2 */
"P8.10", /* gpio2_4 12V_LOAD4_EN */
"P8.11", /* gpio1_13 GPIO3 */
"P8.12", /* gpio1_12 12V_LOAD3_EN */
"P8.13", /* gpio0_23 GPIO4 */
"P8.14", /* gpio0_26 12V_LOAD2_EN */
"P8.15", /* gpio1_15 GPIO5 */
"P8.16", /* gpio1_14 12V_LOAD1_EN */
"P8.17", /* gpio0_27 GPIO6 */
"P8.26", /* gpio1_29 ONE-WIRE */
"P8.37", /* uart5_txd */
"P8.38", /* uart5_rxd */
"P9.11", /* uart4_rxd_mux2 */
"P9.12", /* gpio1_28 LCD_DC */
"P9.13", /* uart4_txd_mux2 */
"P9.14", /* gpio1_18 LCD_BKLT_EN */
"P9.16", /* gpio1_19 LCD_RESET */
"P8.17", /* i2c1_scl */
"P8.18", /* i2c1_sda */
"P9.19", /* i2c2_scl */
"P9.20", /* i2c2_sda */
"P9.21", /* uart2_txd */
"P9.22", /* uart2_rxd */
"P9.24", /* uart1_txd */
"P9.26", /* uart1_rxd */
"P9.27", /* gpio3_19 SOLAR_ENABLE */
"P9.28", /* spi1_cs0 */
"P9.29", /* spi1_d0 */
"P9.30", /* spi1_d1 */
"P9.31", /* spi1_sclk */
"P9.33", /* AIN4 SOLAR_VOLTAGE */
"P9.35", /* AIN6 SOLAR_CURRENT */
"P9.36", /* AIN5 AIN5 */
"P9.37", /* AIN2 SUPPLY_CURRENT */
"P9.38", /* AIN3 AIN3 */
"P9.39", /* AIN0 SUPPLY_VOLTAGE */
"P9.40", /* AIN1 AIN1 */
/* the hardware ip uses */
"gpio2_2",
"gpio2_3",
"gpio2_5",
"gpio2_4",
"gpio1_13",
"gpio1_12",
"gpio0_23",
"gpio0_26",
"gpio1_15",
"gpio1_14",
"gpio0_27",
"gpio1_29",
"uart5",
"uart4",
"gpio1_28",
"gpio1_18",
"gpio1_19",
"i2c1",
"i2c2",
"uart2",
"uart1",
"gpio3_19",
"spi1",
"tscadc";
fragment@0 {
target = <&am33xx_pinmux>;
__overlay__ {
bb_spi1_pins: pinmux_bb_spi1_pins {
pinctrl-single,pins = <
0x190 0x33 /* mcasp0_aclkx.spi1_sclk, INPUT_PULLUP | MODE3 */
0x194 0x33 /* mcasp0_fsx.spi1_d0, INPUT_PULLUP | MODE3 */
0x198 0x13 /* mcasp0_axr0.spi1_d1, OUTPUT_PULLUP | MODE3 */
0x19c 0x13 /* mcasp0_ahclkr.spi1_cs0, OUTPUT_PULLUP | MODE3 */
0x164 0x12 /* eCAP0_in_PWM0_out.spi1_cs1 OUTPUT_PULLUP | MODE2 */
>;
};
bb_i2c1_pins: pinmux_bb_i2c1_pins {
pinctrl-single,pins = <
0x15c 0x72 /* spi0_cs0.i2c1_scl, SLEWCTRL_SLOW | INPUT_PULLUP | MODE2 */
0x158 0x72 /* spi0_d1.i2c1_sda, SLEWCTRL_SLOW | INPUT_PULLUP | MODE2 */
>;
};
bb_i2c2_pins: pinmux_bb_i2c2_pins {
pinctrl-single,pins = <
0x17c 0x73 /* uart1_rtsn.i2c2_scl, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */
0x178 0x73 /* uart1_ctsn.i2c2_sda, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */
>;
};
bb_uart1_pins: pinmux_bb_uart1_pins {
pinctrl-single,pins = <
0x184 0x00 /* P9.24 uart1_txd.uart1_txd | MODE0 OUTPUT */
0x180 0x20 /* P9.26 uart1_rxd.uart1_rxd | MODE0 INPUT */
>;
};
bb_uart2_pins: pinmux_bb_uart2_pins {
pinctrl-single,pins = <
0x150 0x21 /* P9.22 spi0_sclk.uart2_rxd | MODE1 INPUT */
0x154 0x01 /* P9.21 spi0_d0.uart2_txd | MODE1 OUTPUT */
>;
};
bb_uart4_pins: pinmux_bb_uart4_pins {
pinctrl-single,pins = <
0x070 0x26 /* P9.11 gpmc_wait0.uart4_rxd | MODE6 INPUT */
0x074 0x06 /* P9.13 gpmc_wpn.uart4_txd | MODE6 OUTPUT */
>;
};
bb_uart5_pins: pinmux_bb_uart5_pins {
pinctrl-single,pins = <
0x0c4 0x24 /* P8.38 lcd_data8.uart5_rxd | MODE4 INPUT */
0x0c0 0x04 /* P8.37 lcd_data9.uart5_txd | MODE4 OUTPUT */
>;
};
bb_gpio_pins: pinmux_bb_gpio_pins {
pinctrl-single,pins = <
0x090 0x27 /* P8.7 gpmc_advn_ale.gpio2_2 RX_ENABLE | MODE7 */
0x094 0x07 /* P8.8 gpmc_oen_ren.gpio2_3 MODE7 */
0x09c 0x27 /* P8.9 gpmc_ben0_cle.gpio2_5 RX_ENABLE | MODE7 */
0x098 0x07 /* P8.10 gpmc_wen.gpio2_4 MODE7 */
0x034 0x27 /* P8.11 gpmc_ad13.gpio1_13 RX_ENABLE | MODE7 */
0x030 0x07 /* P8.12 gpmc_ad12.gpio1_12 MODE7 */
0x024 0x27 /* P8.13 gpmc_ad9.gpio0_23 RX_ENABLE | MODE7 */
0x028 0x07 /* P8.14 gpmc_ad10.gpio0_26 MODE7 */
0x03c 0x27 /* P8.15 gpmc_ad15.gpio1_15 RX_ENABLE | MODE7 */
0x038 0x07 /* P8.16 gpmc_ad14.gpio1_14 MODE7 */
0x02c 0x27 /* P8.17 gpmc_ad11.gpio0_27 RX_ENABLE | MODE7 */
0x07c 0x37 /* P8.26 gpmc_csn0.gpio1_29 RX_ENABLE | MODE7 */
0x078 0x07 /* P9.12 gpmc_ben1.gpio1_28 MODE7 */
0x048 0x07 /* P9.14 gpmc_a2.gpio1_18 MODE7 */
0x04c 0x07 /* P9.16 gpmc_a3.gpio1_19 MODE7 */
0x1a4 0x07 /* P9.27 mcasp0_fsr.gpio3_19 MODE7 */
>;
};
bb_onewire_pins: pinmux_bb_onewire_pins {
pinctrl-single,pins = <
0x7c 0x37 /* gpio1_29, RX_ENABLE | MODE 7 */ >;
};
};
};
fragment@1 {
target = <&spi1>; /* spi1 is numbered correctly */
__overlay__ {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&bb_spi1_pins>;
#address-cells = <1>;
#size-cells = <0>;
/* add any spi devices connected here */
/* note that you can do direct SPI via spidev now */
spi1_0{
#address-cells = <1>;
#size-cells = <0>;
compatible = "spidev";
reg = <0>;
spi-max-frequency = <16000000>;
spi-cpol;
spi-cpha;
};
spi1_1{
#address-cells = <1>;
#size-cells = <0>;
compatible = "spidev";
reg = <1>;
spi-max-frequency = <16000000>;
spi-cpol;
spi-cpha;
};
};
};
fragment@2 {
target = <&i2c1>;
__overlay__ {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&bb_i2c1_pins>;
/* this is the configuration part */
clock-frequency = <100000>;
#address-cells = <1>;
#size-cells = <0>;
/* add any i2c devices on the bus here */
};
};
fragment@3 {
target = <&i2c2>;
__overlay__ {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&bb_i2c2_pins>;
/* this is the configuration part */
clock-frequency = <100000>;
#address-cells = <1>;
#size-cells = <0>;
/* add any i2c devices on the bus here */
};
};
fragment@4 {
target = <&uart1>;
__overlay__ {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&bb_uart1_pins>;
};
};
fragment@5 {
target = <&uart2>;
__overlay__ {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&bb_uart2_pins>;
};
};
fragment@6 {
target = <&uart4>;
__overlay__ {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&bb_uart4_pins>;
};
};
fragment@7 {
target = <&uart5>;
__overlay__ {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&bb_uart5_pins>;
};
};
fragment@8 {
target = <&tscadc>;
__overlay__ {
status = "okay";
adc {
ti,adc-channels = <0 1 2 3 4 5 6>;
ti,chan-step-avg = <0x16 0x16 0x16 0x16 0x16 0x16 0x16>;
ti,chan-step-opendelay = <0x98 0x98 0x98 0x98 0x98 0x98 0x98>;
ti,chan-step-sampledelay = <0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
};
};
};
fragment@9 {
target = <&ocp>;
__overlay__ {
onewire@0 {
status = "okay";
compatible = "w1-gpio";
pinctrl-names = "default";
pinctrl-0 = <&bb_onewire_pins>;
gpios = <&gpio1 29 0>;
};
};
};
I'm also curious as to whether the Pin Usage section of the eeprom is actually used - perhaps only relevant when a second cape is plugged in, and the eeprom checked for resource clashes?
Dean Claxton
Apr 11, 2017, 2:02:14 AM4/11/17
to BeagleBoard
Oh - I'm using the latest Debian build from the 19th March 2017.
Cheers,
Dean
Reply all
Reply to author
Forward
0 new messages