Weekly Progress Report Thread: Reference Design For A GPIO-based Parallel Bi-Directional Bus

[Pranav Kumar]

Hello,

This is a week #0 status update for the GSoC 2019 project  Reference Design For A GPIO-based Parallel Bi-Directional Bus

• Accomplishments:
• First I made an introductory youtube video of my project
• Purchased hardware related to this project like 8-bit logic analzer ,logic level converter 
• Understand about the code structure on making kernel module Beagleboard and understanding the beaglelogic code docs 
• Read a little bit about kernel module development from this page .
• I will also keep track of my work on this elinux wiki page for better representation of the developed work. 
• Resolutions to blockers:
• Get back to work as soon as my exams get over 
• On-going blockers:
• I have my end semester exam till 31 may 2019 
• Plans for the next week:
• To get on track and complete my first week task as soon as possible and discuss more of my work with my mentor.

This thread will be used for weekly progress updates of the project or you can follow up the above listed wiki page for more detailed update on the project.

[Pranav Kumar]

Hello,

This is a week #1 status update for the GSoC 2019 project  Reference Design For A GPIO-based Parallel Bi-Directional Bus

• Accomplishments:
• Studied the kernel module development and done with the hardware setup.
• studied the beagle logic code and mail my queries to the mentors. 
• studying the PRU assembly guides provided by mentors
• To check more reviewed of my work on this elinux wiki page .
• Resolutions to blockers:
• Complete the video using assembly code in pru as mention by mentors 
• On-going blockers:
• No Blockers

• Plans for the next week:

• To make the most of  pru assembly program and and test it on the board and complete the working video. 

Regards

Pranav Kumar

[Pranav Kumar]

Hello,

This is a week #2 status update for the GSoC 2019 project  Reference Design For A GPIO-based Parallel Bi-Directional Bus

Accomplishments:

• able to run example assembly code on pru 
• mail the mentor about the pru memory mapping 
• updated the github with more easy to run code in a single folder 
• To check more reviewed work on this elinux wiki page .

• Resolutions to blockers:

• make the program in assembly and control the shift register in accordance with that
• under the the assembly code more clearly and memory mapping. 

On-going blockers:

• memory mapping of the registers

Plans for the next week:

• complete assembly code as far as possible and start with the kernel module development

Regards 

Pranav Kumar

[Jason Kridner]

On Mon, Jun 10, 2019 at 3:17 PM Pranav Kumar <kpran...@gmail.com> wrote:

Hello,

This is a week #2 status update for the GSoC 2019 project  Reference Design For A GPIO-based Parallel Bi-Directional Bus

Accomplishments:

• able to run example assembly code on pru 
• mail the mentor about the pru memory mapping 
• updated the github with more easy to run code in a single folder 
• To check more reviewed work on this elinux wiki page .

• Resolutions to blockers:

• make the program in assembly and control the shift register in accordance with that
• under the the assembly code more clearly and memory mapping. 

On-going blockers:

• memory mapping of the registers

Can you go more into this issue? Are you wondering where GPIOs are mapped? 

Did you clear the SYSCFG[STANDBY_INIT] flag to enable OCP access?

/* Clear SYSCFG[STANDBY_INIT] to enable OCP master port */ CT_CFG.SYSCFG_bit.STANDBY_INIT = 0;

Is https://github.com/beagleboard/cloud9-examples/blob/master/PocketBeagle/TechLab/rgb.pru0c useful as it uses memory mapped GPIO registers?

 

Plans for the next week:

• complete assembly code as far as possible and start with the kernel module development

Regards 

Pranav Kumar

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[Pranav Kumar]

Thanks i will look into it

To view this discussion on the web visit https://groups.google.com/d/msgid/beagleboard-gsoc/CA%2BT6QPmeMWi4Y6_EJ42aObExfyLCQsm5NWgNJ6iWUtPM8ppw8w%40mail.gmail.com.

[Pranav Kumar]

Hello,

This is a week #3 status update for the GSoC 2019 project  Reference Design For A GPIO-based Parallel Bi-Directional Bus

Unfortunately, I forget to update the status of the last week here on the thread  

Accomplishments:hc

• able to run assembly code on the 8 bit shift register  74hc595  
• made a working youtube video for that on the progress playlist : https://www.youtube.com/watch?v=yTIs10-VrbM
• updated the same code for assembly on the github : https://github.com/pranav083/pocket_beagle-work/tree/master/1.shift/bb_black

• To check more reviewed work on this elinux wiki page .

• Resolutions to blockers:

• waiting for the reply from the mentor over the progress of the project on the development of the kernel part 
• Mentor still prefer to use r30 and r31 register of pru beacuse of its speed of operation
• working on the device tree different configuration of pins to make the pins work in different modes of pinmux   

On-going blockers:

• Unable to access the pru pins till now in mode mode 6 and mode 5 or the pru r30 and r31 register 
• changing the device tree to make the pru work in the other modes in the pinmux setting(other than mode7 ) which are mode 5 and mode 6 in which their is access of r30 and r31 register.   

Plans for the next week:

• start with the kernel module development and understanding the working of the beaglelogic (espically the kernel and firmware folder in the source code ) 

Regards 

Pranav Kumar

[Pranav Kumar]

Hello,

This is a week #3 status update for the GSoC 2019 project  Reference Design For A GPIO-based Parallel Bi-Directional Bus

Unfortunately, I forget to update the status of the last week here on the thread  

Accomplishments:

• Studied  the datasheet of the am335xx from : https://elinux.org/images/6/65/Spruh73c.pdf  as said by @ds2 to understand better about the pru on the beagleboard and for the better understanding of beaglelogic file 
• working on the link provided by @hendersa : https://github.com/RobertCNelson/dtb-rebuilder   
• and as suggested making timing diagram in the mean time. 
• made a quick blog on the previous work as suggested by @ds2 on the pin used and a easy go through guide for other and made wiki on that especially  pru application, its programming etc.

• To check more reviewed work on this elinux wiki page .

• Resolutions to blockers:

• Completing the documentation of the work till now done espically the pru problem  problem that can be face 
• working on the kernel module development part by getting referrence from the beaglelogic 

On-going blockers:

• understanding the files in the beaglelogic  for making will discuss with @abhisek_on that
• as @hendersa suggest to move on the projetct with the mode 7 only but still i tried other modes by making different changes on the device tree but still no luck on that : https://gist.github.com/pranav083/fe3916cd4a97e8b9a823d82c82458d82 

Plans for the next week:

• To start working with the beaglelogic codebase as it had already have some work done for this project 
• making my own .dts file for the pru use cases that can be helpful in the further development of the project

Regards 

Pranav Kumar

[Pranav Kumar]

Hello,

This is a week #5 status update for the GSoC 2019 project  Reference Design For A GPIO-based Parallel Bi-Directional Bus 

Accomplishments:

• Done the most of the documentation work ,made the circuit and commit all the changes on the github page : https://github.com/pranav083/pocket_beagle-work/blob/circuit/2.shift_74hc299/BB_Black/
  
• Submitted three video on the playlist on my youtube page : https://www.youtube.com/playlist?list=PLttoix_9Us2yHM4zNr08ynm4iwXZTgxam of the work done on the 74hc299 shift register
• made a blog on how to upload assembly code using the prussdrv technique on the wiki progress page : https://elinux.org/Beagleboard_gsoc_2019_bi-directional_progress 
• worked on the documentation part, circuit etc.

• Resolutions to blockers:
• • Discuss with the mentor about the timing diagram of the output as it some time give wrong signal 

On-going blockers:

•  no blocker for now

Plans for the next week:

• make every day update on the project and to complete the firmware part if any left as suggested by the mentor 
• and as @hendersa told doing the work with the beaglelogic 

Regards 

Pranav Kumar

[Pranav Kumar]

it was the update of the week #4 

[Pranav Kumar]

Hello,

This is a week #6 status update for the GSoC 2019 project  Reference Design For A GPIO-based Parallel Bi-Directional Bus 

Accomplishments:

• Tested the signal of the shift register and its correctness on the term of input and output for controlling pins and latching .
• Have a voice talk with @zeekhuge about the development of the project 
• Earlier for the latch storage purpose used the 4066 ic for the latch controlled of the output
• Figured out the anamoly in the circuit and effect of enable on the IC as suggested by @hendersa 
• Much this week as i was travelling from my Chandigarh to IIT Hyderabad as our team get selected as finalist in the Smart India Hackathon (Funded by Govt. Of India ) . So, I was not been able to update on my progress page.

• Resolutions to blockers:

• Communicate between multiple controller  using the shift register
• for today communicate with easy prototyping micro controller with register using aync communication with beaglebones as master and slaves.

On-going blockers:

• i am outside of station so their may came a delay for one day or two when i will be travelling back to my hostel 

Plans for the next week:

• Must complete the the applications suggested to get the things back on track 

Regards 

Pranav Kumar

[Pranav Kumar]

Hello,

This is a week #6 status update for the GSoC 2019 project  Reference Design For A GPIO-based Parallel Bi-Directional Bus 

Accomplishments:

• Found the solution to high frequency signal that are interfering the code thanks to @zmatt 
• made the video with the corrected code : https://youtu.be/R3kSgY7nwpk
• code is here : https://github.com/pranav083/pocket_beagle-work/blob/wip/pru_wip/74hc299_10_v1.p
• updated my on ongoing problem with mentors

• Resolutions to blockers:

• getting the code ready for the slave devices. 

On-going blockers:

• voltage that i achieved on the pins during the high state is often low to change the output differentiate between high and low level logic signal. Probably testing the circuit to make it right as was not able to find the voltage drop.

Plans for the next week:

• working on the cross communication part of the between two beaglebone and further extending its to other platforms also

Regards 

Pranav Kumar

[Pranav Kumar]

its the week #7 update of the work . and one thing that i miss in the resolution to the blocker is the documentation part. Also , I am back to  my hostel .  

[Pranav Kumar]

Hello,

This is a week #8 status update for the GSoC 2019 project  Reference Design For A GPIO-based Parallel Bi-Directional Bus 

Accomplishments:

• remove the logic level converter as suggested by @ds2
• Made the code master and slave ic that can tranfer data at configurable bits length :https://github.com/pranav083/pocket_beagle-work/tree/wip/6.shift_74hc299_bi/v2
• earlier made a different code with handshaking of signal with only using the shift register for communication which comes out to be slow and unrecommended approach as said by @hendersa :https://github.com/pranav083/pocket_beagle-work/tree/wip/6.shift_74hc299_bi/v1
• updated my on ongoing problem with mentors regading the ssh connection refusal by BBB

• Resolutions to blockers:

• made the video and waiting for further instructions by the mentors 

On-going blockers:

• some time the beaglebones are accessible via  ssh . If connected , I have hard time doing the connection with the BBBs  

Plans for the next week:

• optimization of the code as the basic protocol for bi-directional bus is made  
• have to update all the work done this week on the progress page with small documentation

Regards 

Pranav Kumar