#include <bcm2835.h>int main(void){ if (!bcm2835_init()) return 1; bcm2835_gpio_ren(26); bcm2835_close(); return 0;}
gdb: Reading symbols from ./irq_test...done.(gdb) b 4Breakpoint 1 at 0x1078c: file irq_test.c, line 4.(gdb) runStarting program: /home/pi/irq_test
Breakpoint 1, main () at irq_test.c:44 if (!bcm2835_init())(gdb) n6 bcm2835_gpio_ren(26);(gdb) sbcm2835_gpio_ren (pin=26 '\032') at bcm2835.c:351351 volatile uint32_t* paddr = bcm2835_gpio + BCM2835_GPREN0/4 + pin/32;(gdb) s353 uint32_t value = 1 << shift;(gdb) s351 volatile uint32_t* paddr = bcm2835_gpio + BCM2835_GPREN0/4 + pin/32;(gdb) s353 uint32_t value = 1 << shift;(gdb) s354 bcm2835_peri_set_bits(paddr, value, value);(gdb) sbcm2835_peri_set_bits (paddr=0xb4e7904c, value=67108864, mask=67108864) at bcm2835.c:238238 {(gdb) s239 uint32_t v = bcm2835_peri_read(paddr);(gdb) sbcm2835_peri_read (paddr=paddr@entry=0xb4e7904c) at bcm2835.c:170170 if (debug)(gdb) s177 __sync_synchronize();(gdb) s178 ret = *paddr;(gdb) s179 __sync_synchronize();(gdb) s180 return ret;(gdb) sbcm2835_peri_set_bits (paddr=0xb4e7904c, value=<optimized out>, mask=67108864) at bcm2835.c:241241 bcm2835_peri_write(paddr, v);(gdb) s242 }(gdb) s241 bcm2835_peri_write(paddr, v);(gdb) sbcm2835_peri_write (paddr=0xb4e7904c, value=67108864) at bcm2835.c:208208 if (debug)(gdb) s214 __sync_synchronize();(gdb) s215 *paddr = value;(gdb) s
Op 16 jun. 2018, om 20:12 heeft tccio...@gmail.com het volgende geschreven:Having made a mistake to (test) "set" ALL 50 plus GPIO 50 plus pins = manipulating wrong pin can lead to hair loss.
kernel:[ xxx.xxxxxx] Disabling IRQ #73
(gdb) stepbcm2835_peri_write (paddr=0xb4e7904c, value=4) at bcm2835.c:207207 {(gdb) step208 if (debug)(gdb) step207 {(gdb) step208 if (debug)(gdb) step214 __sync_synchronize();(gdb) step215 *paddr = value;(gdb) step
Message from syslogd@nodeC at Jun 18 06:22:02 ... kernel:[ 605.788098] Disabling IRQ #73216 __sync_synchronize();(gdb) step218 }(gdb)
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In particular, it may be a gcc bug when invoking __sync_synchronized().That is pissible
The __sync_synchronized is implemented as : mcr 15, 0, r0, cr7, cr10, {5} which is a dmb().
This should only be done on a Raspberry Pi Model 1 (first
output). On all other boards it should use the native dmb
instruction (second output).
The compiler options for the second output is : -mfpu=neon-vfpv4 -march=armv7-a -mtune=cortex-a7
I have not tested the library, yet, with these native platform
settings. So I cannot tell if it is really a solution.
Greets. Arjan
http://www.raspberrypi-dmx.org/
00000150 <bcm2835_peri_read>:
150: e92d4800 push {fp, lr}
154: e28db004 add fp, sp, #4
158: e24dd010 sub sp, sp, #16
15c: e50b0010 str r0, [fp, #-16]
160: e59f3040 ldr r3, [pc, #64] ; 1a8
<bcm2835_peri_read+0x58>
164: e5d33000 ldrb r3, [r3]
168: e3530000 cmp r3, #0
16c: 0a000004 beq 184
<bcm2835_peri_read+0x34>
170: e59f0034 ldr r0, [pc, #52] ; 1ac
<bcm2835_peri_read+0x5c>
174: e51b1010 ldr r1, [fp, #-16]
178: ebfffffe bl 0 <printf>
17c: e3a03000 mov r3, #0
180: ea000005 b 19c
<bcm2835_peri_read+0x4c>
184: ee070fba mcr
15, 0, r0, cr7, cr10, {5}
188: e51b3010 ldr r3, [fp, #-16]
18c: e5933000 ldr r3, [r3]
190: e50b3008 str r3, [fp, #-8]
194: ee070fba mcr 15, 0, r0, cr7,
cr10, {5}
198: e51b3008 ldr r3, [fp, #-8]
19c: e1a00003 mov r0, r3
1a0: e24bd004 sub sp, fp, #4
1a4: e8bd8800 pop {fp, pc}
00000150 <bcm2835_peri_read>:
150: e92d4800 push {fp, lr}
154: e28db004 add fp, sp, #4
158: e24dd010 sub sp, sp, #16
15c: e50b0010 str r0, [fp, #-16]
160: e3003000 movw r3, #0
164: e3403000 movt r3, #0
168: e5d33000 ldrb r3, [r3]
16c: e3530000 cmp r3, #0
170: 0a000005 beq 18c
<bcm2835_peri_read+0x3c>
174: e3000000 movw r0, #0
178: e3400000 movt r0, #0
17c: e51b1010 ldr r1, [fp, #-16]
180: ebfffffe bl 0 <printf>
184: e3a03000 mov r3, #0
188: ea000005 b 1a4
<bcm2835_peri_read+0x54>
18c: f57ff05f dmb sy
190: e51b3010 ldr r3, [fp, #-16]
194: e5933000 ldr r3, [r3]
198: e50b3008 str r3, [fp, #-8]
19c: f57ff05f dmb sy
1a0: e51b3008 ldr r3, [fp, #-8]
1a4: e1a00003 mov r0, r3
1a8: e24bd004 sub sp, fp, #4
1ac: e8bd8800 pop {fp, pc}
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/* RPi 2 is ARM v7, and has DMB instruction for memory barriers. Older RPis are ARM v6 and don't, so a coprocessor instruction must be used instead. However, not all versions of gcc in all distros support the dmb assembler instruction even on conmpatible processors. This test is so any ARMv7 or higher processors with suitable GCC will use DMB.*/#if __ARM_ARCH >= 7#define BCM2835_HAVE_DMB#endif
RH_RF95::setModeTx (this=0x270c8 <rf95>) at ../../../RH_RF95.cpp:403403 if (_mode != RHModeTx)(gdb) s405 spiWrite(RH_RF95_REG_01_OP_MODE, RH_RF95_MODE_TX);(gdb) n406 spiWrite(RH_RF95_REG_40_DIO_MAPPING1, 0x40); // Interrupt on TxDone(gdb) n <---Hangs here when next stepping line 406
RHSPIDriver::spiWrite (this=0x270c8 <rf95>, reg=64 '@', val=64 '@') at ../../../RHSPIDriver.cpp:4545 uint8_t status = 0;(gdb) n46 RPI_CE0_CE1_FIX;(gdb) n48 digitalWrite(_slaveSelectPin, LOW);(gdb) n49 status = _spi.transfer(reg | RH_SPI_WRITE_MASK); // Send the address with the write mask on(gdb) n50 _spi.transfer(val); // New value follows(gdb) n <----It hangs here when next stepping line 50
bcm2835_peri_write_nb (value=64, paddr=0xb4e89004) at bcm2835.c:223223 if (debug)(gdb) s230 *paddr = value;(gdb) s <-----It hangs here when I step instruction 230
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#include <bcm2835.h>
#include <stdio.h>
#define RF_IRQ_PIN RPI_GPIO_P1_07 // IRQ on GPIO04 so P1 connector pin #07
int main(int argc, char **argv)
{
// If you call this, it will not actually access the GPIO
if (!bcm2835_init())
return 1;
// Set RPI pin to be an input
bcm2835_gpio_fsel(RF_IRQ_PIN, BCM2835_GPIO_FSEL_INPT);
// with a puldown
bcm2835_gpio_set_pud(RF_IRQ_PIN, BCM2835_GPIO_PUD_DOWN);
// And a rising edge detect enable
bcm2835_gpio_ren(RF_IRQ_PIN);
while (1) {
// we got it ?
if (bcm2835_gpio_eds(RF_IRQ_PIN)) {
// Now clear the eds flag by setting it to 1
bcm2835_gpio_set_eds(RF_IRQ_PIN);
printf("Rising event detect for pin GPIO%d\n", RF_IRQ_PIN);
}
// wait a bit
bcm2835_delay(5);
}
bcm2835_close();
return 0;
}