heres the init function:
int bcm2835_aux_spi_begin(void)
{
volatile uint32_t* enable = bcm2835_aux + BCM2835_AUX_ENABLE/4;
// volatile uint32_t* cntl0 = bcm2835_spi1 + BCM2835_AUX_SPI_CNTL0/4;
// volatile uint32_t* cntl1 = bcm2835_spi1 + BCM2835_AUX_SPI_CNTL1/4;
volatile uint32_t* cntl0 = bcm2835_spi2 + BCM2835_AUX_SPI_CNTL0/4;
volatile uint32_t* cntl1 = bcm2835_spi2 + BCM2835_AUX_SPI_CNTL1/4;
if (bcm2835_spi2 == MAP_FAILED) // bcm2835_spi1 auf bcm2835_spi2 - raffimod
return 0; /* bcm2835_init() failed, or not root */
/* Set the SPI pins to the Alt 4 function to enable SPI1 access on them */
// bcm2835_gpio_fsel(RPI_V2_GPIO_P1_36, BCM2835_GPIO_FSEL_ALT4); /* SPI1_CE2_N */
// bcm2835_gpio_fsel(RPI_V2_GPIO_P1_35, BCM2835_GPIO_FSEL_ALT4); /* SPI1_MISO */
// bcm2835_gpio_fsel(RPI_V2_GPIO_P1_38, BCM2835_GPIO_FSEL_ALT4); /* SPI1_MOSI */
// bcm2835_gpio_fsel(RPI_V2_GPIO_P1_40, BCM2835_GPIO_FSEL_ALT4); /* SPI1_SCLK */
//raffimod mit CM3 pins
bcm2835_gpio_fsel(CM3_BANK1_GPIO43, BCM2835_GPIO_FSEL_ALT4); /* SPI2_CE0_N */
bcm2835_gpio_fsel(CM3_BANK1_GPIO40, BCM2835_GPIO_FSEL_ALT4); /* SPI2_MISO */
bcm2835_gpio_fsel(CM3_BANK1_GPIO41, BCM2835_GPIO_FSEL_ALT4); /* SPI2_MOSI */
bcm2835_gpio_fsel(CM3_BANK1_GPIO42, BCM2835_GPIO_FSEL_ALT4); /* SPI2_SCLK */
//bcm2835_aux_spi_setClockDivider(bcm2835_aux_spi_CalcClockDivider(1000000)); // Default 1MHz SPI
bcm2835_aux_spi_setClockDivider(bcm2835_aux_spi_CalcClockDivider(10000000)); // 10MHz SPI
// bcm2835_peri_write(enable, BCM2835_AUX_ENABLE_SPI0);
bcm2835_peri_write(enable, BCM2835_AUX_ENABLE_SPI1); // aka spi2 - raffimod
bcm2835_peri_write(cntl1, 0);
bcm2835_peri_write(cntl0, BCM2835_AUX_SPI_CNTL0_CLEARFIFO);
return 1; /* OK */
}
the working 16bit write function:
// raffimodded - aux_spi_write function - works for 16bit
void bcm2835_aux_spi_write(uint16_t data)
{
volatile uint32_t* cntl0 = bcm2835_spi2 + BCM2835_AUX_SPI_CNTL0/4; // raffimod - auf _spi2 angepasst
volatile uint32_t* cntl1 = bcm2835_spi2 + BCM2835_AUX_SPI_CNTL1/4; // raffimod - auf _spi2 angepasst
volatile uint32_t* stat = bcm2835_spi2 + BCM2835_AUX_SPI_STAT/4; // raffimod - auf _spi2 angepasst
volatile uint32_t* io = bcm2835_spi2 + BCM2835_AUX_SPI_IO/4; // raffimod - auf _spi2 angepasst
uint32_t _cntl0 = (spi1_speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT);
_cntl0 |= BCM2835_AUX_SPI_CNTL0_CS0_N; // raffimod - von CS2_N auf CS0_N angepasst
_cntl0 |= BCM2835_AUX_SPI_CNTL0_ENABLE;
_cntl0 |= BCM2835_AUX_SPI_CNTL0_MSBF_OUT;
_cntl0 |= 16; // Shift length
bcm2835_peri_write(cntl0, _cntl0);
bcm2835_peri_write(cntl1, BCM2835_AUX_SPI_CNTL1_MSBF_IN);
// room for improvement - disable the simultateous read from the MISO - raffimod to be
while (bcm2835_peri_read(stat) & BCM2835_AUX_SPI_STAT_TX_FULL)
;
bcm2835_peri_write(io, (uint32_t) data << 16);
}
and the nonworking 8 bit transfer function:
// raffimod - extra transfer function for 8 bit data
void bcm2835_aux_spi_transfer(uint8_t data)
{
volatile uint32_t* cntl0 = bcm2835_spi2 + BCM2835_AUX_SPI_CNTL0/4; // raffimod - auf _spi2 angepasst
volatile uint32_t* cntl1 = bcm2835_spi2 + BCM2835_AUX_SPI_CNTL1/4; // raffimod - auf _spi2 angepasst
volatile uint32_t* stat = bcm2835_spi2 + BCM2835_AUX_SPI_STAT/4; // raffimod - auf _spi2 angepasst
volatile uint32_t* io = bcm2835_spi2 + BCM2835_AUX_SPI_IO/4; // raffimod - auf _spi2 angepasst
uint32_t _cntl0 = (spi1_speed << BCM2835_AUX_SPI_CNTL0_SPEED_SHIFT);
_cntl0 |= BCM2835_AUX_SPI_CNTL0_CS0_N; // raffimod - von CS2_N auf CS0_N angepasst
_cntl0 |= BCM2835_AUX_SPI_CNTL0_ENABLE;
_cntl0 |= BCM2835_AUX_SPI_CNTL0_MSBF_OUT;
//_cntl0 |= 8; // Shift length
_cntl0 |= BCM2835_AUX_SPI_CNTL0_VAR_WIDTH;
bcm2835_peri_write(cntl0, _cntl0);
bcm2835_peri_write(cntl1, BCM2835_AUX_SPI_CNTL1_MSBF_IN);
while (bcm2835_peri_read(stat) & BCM2835_AUX_SPI_STAT_TX_FULL)
;
bcm2835_peri_write(io, (uint32_t) data << 8);
}
also here and there were some additional defines needed. and of course the different pins to use. and the baseadress offset (which is already defined in v1.60)