Multiple positions with Semi conductor client : Physical Design Engineer, RTL Engineer, Layout Engineer, ASIC Verification
Chandu K
1) ASIC Verification || Santa Clara CA
Job Responsibilities:
· Architect and develop verification environment, testbench components, and reference models for designs at block and system level.
· Develop a comprehensive test plan and implement test cases.
· Verify design in block and chip-level environments using directed and constrained random testing, assertion-based verification, formal analysis, and functional verification.
· Perform RTL code coverage, assertion coverage, and gate-level simulations.
· Drive and adopt new verification methodologies and flows for efficiency improvements.
· Job Requirements:
· BS in Electrical Engineering, Computer Science, or related field with 15+ years of Industry experience or MS in Electrical Engineering, Computer Science, or related field preferred with 12+ years industry experience.
· Experience in verifying designs at block and system level.
· Experience using SystemVerilog and UVM.
· Strong experience in ASIC design verification flows and DV methodologies.
· Experience working with cross-functional teams to deliver ASICs from architecture to FCS.
· Strong programming and scripting language (C/C++/Python etc.) capability.
· Strong and independent design debugging capability.
· Domain knowledge of Ethernet, PCIe, and Switch Fabric is desirable.
· Good problem-solving skills and the passion to take on challenges.
· Highly motivated and able to work independently and as a team member.
2) Lead SoC Physical Design Engineer
Job Summary
We are looking for an experienced Lead SoC Physical Design Engineer with strong hands-on expertise across advanced technology nodes (including 5nm). The ideal candidate will lead Physical Design activities from synthesis through GDSII and collaborate closely with CAD, Methodology, and IP teams to ensure successful tape-outs.
Required Skill
· Physical Design, preferably with methodology/flow experience.
· Strong understanding in the RTL2GDSII flow or design implementation in leading process technologies. Good understanding of the RTL2GDSIl concepts related to synthesis, place & route, CTS, timing convergence, layout closure.
· Expertise on high frequency design methodologies. Good knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. Working experience with tools like ICC2/Innovus, Primetime/Tempus/Seahawk etc used in the RTL2GDSIl implementation.
· Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred. Well versed with timing constraints, STA, IR and ECO timing closure.
· Strong algorithmic thinking with good automation skills in PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools. Python will be helpful too.
· Ability to multi-task and flexibility to work in global environment.
· Good communication skills and strong motivation, Strong analytical & Problem Solving skills
· Willingness to learn and master new techniques quickly
· Innovate and drive changes across teams & workflows
3. RTL Engineer|| Santa Clara CA
Job Title: Lint/CDC Design Lead
· Experience: 5+ years of relevant experience
· Strong in digital IP design using RTL for lower technology nodes [3/4/7nm].
· Experience in micro architect and implementation of complex IP blocks for high-speed designs.
· Optimization of digital logic by analysing timing reports at various stages of ASIC design cycles and defining solutions for path.
· Experience in developing modules for AXI4/5, CHI interfaces.
· Experience in RTL implementation of PCIe/CXL, Ethernet, UCIE , UAL, DDR/HBM/LPDDR and AXI bridging layer.
· Experience in the closure of RTL blocks with quality checks, CDC/RDC/Lint.
· Define and propose innovative solutions to the problem.
· Good team player, proactive in communications, lead proposed solutions to closure.
· Documentation on design approaches, discuss it within the team, come up with conclusive approaches and drive it.
· Co-work with other functional teams on project
4. Layout Engineer, || Santa Clara CA
Here is job description
· You will drive the Layout design of the project from Floorplan, design and development till the project release.
· You will drive the Layout design of the project from Floorplan till the project release and lead the project throughout the entire design and development phase.
· Strong Knowledge and experience in layout design of high-speed blocks in latest Tech Nodes (2nm, 3nm, 5nm)
· You will drive the design and development of high-quality analog and mixed-signal layouts.
· Your expertise will ensure the successful implementation of CMOS and FINFET technologies.
· Through effective troubleshooting, you will contribute to achieving clean physical verification results.
· Your attention to detail will ensure that layout documents meet quality standards and deadlines.
· By managing project schedules and milestones, you will help deliver projects on time.
· Your collaboration with cross-functional teams will enhance project success and innovation
What You’ll Need:
· Bachelor's or Master's degree in Electrical Engineering or a related field.
· Experience in Analog and Mixed Signal Circuit Layout.
· Proficiency in Analog Layout Flow from device placement to GDS release.
· Strong knowledge of CMOS and FINFET technologies and semiconductor device physics.
· Experience with EDA tools for custom mixed-signal layout flows.
· Understanding of CMOS fabrication technology and deep sub-micron effects on layout.
· Knowledge of electro-migration, reliability concepts, and ESD/LUP concepts as applied to layout.
· Passion for learning and exploring new techniques.
| CHANDU.K |
Manager-BS | Broadpeak Systems Inc 630 Freedom Business Center Dr, Suite 300, Unit #82 Hangouts: chandu...@gmail.com |