Synopsys Design Compiler Crack
Laurice Whack
.synopsys_dc.setup Don't miss this one! Make sure the file begins with a period. Copy it to your home dir (but then you can't customize it for individual runs, which is probably ok), or your working dir (make sure you copy it when you start a new dir). If you have a .synopsys_dc.setup file in your home directory (from ECE 180B for example), you will likely need to move it or change its name so that DC won't get confused.
Do not edit this file unless you are told you need to. Remember that it appears in linux only with "ls -a" and not just "ls".
Previously, we used the 0.25 um vtvt library.
- vtvt25 is a public-domain standard cell library based on TSMC's 0.25um2.5 V standard CMOS process using MOSIS design rules.The library is much smaller than common commercial libraries, but as adequatefor the area and delay estimation work we will do.The library was made by Dong Ha's group at Virginia Tech and moredetails can be found at theVirginia TechVLSI for Telecommunications web page.
I'm writing a synthesizable VHDL model, which uses RAM of few kilobytes.
Design Compiler can synthesize RAMs only as flip flops, and this size is too
big for that. So, I need to tell it to treat an entity as block box and
prevent it from synthesizing the RAM.I tried doing this by wrapping the "architecture" part of my RAM model
inside --pragma synthesis_off/on pair, but then Synopsys complains:
'SYNC_SRAM' was not identified as a synthetic library module
and could not be successfully elaborated from design library 'WORK'Any idea?
But the sysnthesis tool will NOT instantiate a RAM model. So your design is
without RAM, and any connections to your RAM will be optimized out.
This is not a solution for you. You need to get the right DW ram, or library
of ram from your target library vendor (e.g., LSI if that is your target).
This should allow you to elaborate your design, even though synopsys will
give a warning about not being able to find a model for the RAM... You can
then synthesize, but obviously without taking timing condition into account
of the RAM interface.To make it really clean (read: no warnings during elaborate and
compilation), you need a synopsys .lib library model of the RAM. This .lib
model must be first converted into a .db file. Just use read_lib in
dc_shell. It will complain and give an error that you don't have library
compiler, but you can ignore this error: you can will write out the model
as a DB file. (The error is really about special .lib feature that you
don't need for a black box only model).If you don't have a .lib of the RAM model, then you will have to make one.
Good luck: it is not that difficult, but it will cost you quite a lot of
time. :-]Hope this helps (it has always worked for me...),Tom
The power consumed by the synchronous and asynchronous display controllers was measured, and the asynchronous design consumed about 17% less power than its synchronous counterpart. The area of the asynchronous design was twice that of the synchronous one. Power can be reduced by reducing the dependency of the clock signal in the design by choosing asynchronous logic.
Use "ls" commend to check if "library.lib" is in your synopsys directory. This file contains logical descriptions and timing information for a set of logic gates (cells).The first time you use Synopsys, you probably won't have a cell library yet, so you should use this library as-is. The library file contains definitions for an inverter, nand2, nand3, nand4, nor2, nor3, aoi12, aoi22, oai12, oai22, and d-flip-flop.When you create a cell library in Cadence later on, you will need to modify the Synopsys library file to match your cells.If your cells differ from those in the library file, you may need to change cell names, pin names, and /or logical descriptions in the library file to match; this shouldn't be much of a problem if you pay attention to the Synopsys library file when laying out your cells in Cadence.Timing information is a more advanced subject, so you shouldn't change the given values, although you may want to experiment with changing the reported delays to match those of your cells if time allows.
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