I am new to SystemVerilog and AVM.
Currently I am trying to adopt AVM in the verification of my new
design.
I need to get a byte array from a packed struct.
The following code is what I saw somewhere and wrote in the same
manner.
This will, however, causes deeper hierarchy.
Could anybody help me with a neat code style to do the same job?
Thanks.
Best Regards,
eggice
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typedef struct packed {
bit ht;
bit ec;
bit[5:0] sh_type;
bit rsv;
bit ci;
bit[1:0] eks;
bit rsv2;
bit[10:0] len;
bit[15:0] cid;
bit[7:0] hcs;
} s_gmh;
typedef union packed {
s_gmh gmh_fields;
bit[0:5] [7:0] byte_slice;
} u_gmh;
typedef struct packed {
bit ht;
bit ec;
bit[5:0] sh_type;
bit rsv;
bit ci;
bit[1:0] eks;
bit rsv2;
bit[10:0] len;
bit[15:0] cid;
bit[7:0] hcs;
} s_gmh;
typedef bit[0:5][7:0] byte6x8;
byte6x8 bytes;
s_gmh fields;
bytes = byte6x8'(fields);
The downside is that it's a little less portable in that any change to
the size of the struct can cause issues.
It's working fine since that struct is always fixed size.
It does help to simplify my codes.
Thanks a lot.
Best Regards,
eggice
On 10月8日, 下午9時15分, "dustin.r.john...@gmail.com"