How to write a verification plan?

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Dan Shupe

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Jul 17, 2008, 9:34:40 AM7/17/08

to Advanced Verification Methodology User Group

I am new to AVM, Questa, SystemVerilog, and verification in general,
as is my company. I have been tasked with writing a verification plan
for an FPGA design. There is nothing to use as a template or example.

Where do I begin? I am sort of pioneering the process here, so I want
to get the first one right and set the precedent...

Bahaa Osman

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Jul 17, 2008, 9:58:47 AM7/17/08

to avm-...@googlegroups.com

Hi,

Verification Plan:
There are lots of topics about verification planning on the Verification Guild forum. Here are a few useful links:
http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=2170&highlight=plan
http://verificationguild.com/modules.php?name=Forums&file=viewtopic&p=9624
http://verificationguild.com/modules.php?name=Forums&file=viewtopic&t=2100&highlight=plan

http://www.systemverilog.us/verifplan_cmptsDsgn_Cohen.pdf

Attached is a template if you'd like.

AVM: You are advised to read the Verification cookbook. You can download it from www.mentor.com/go/cookbook. You may want to explore the OVM (www.ovmworld.org) as well since it is based on the AVM with more features and capabilities.

Questa: There are lots of capabilities in Questa regarding linking your verification plan to your simulation, and getting coverage results on your plan. The verification management facility in Questa is a very useful resource for you i guess. You may want to refer to the Questa user manual for more details, or contact your Mentor representative.

Hope this helps.

Bahaa