coverage point for tempral properties

[Essam]

Hi all

I have another question related to coverage group and coverage points
in system verilog.

can we express tempral properties using covergroup or coverpoint in
SV?

i know we can do it using Assertion but i am not sure if we can do as
covergroup.

I have this example of 4by4 switch, I want to check when packet
arrives at the input and when the sender ID = destination ID the pack
should be received at the destination in 4 internal clock cycle ( 3
SWClk)

the assertion property is writen like this

property p1;
bit[7:0] data;
@(posedge MClk) (R0In[7:4]==R0In[3:0], data = Reg_R0) ##4
(R0Out[7:4]==R0Out[3:0]) && R0Out == data;
endproperty


Can we express the above assertion property using covergroup and
coverpoint ? if so how and if not why ??


Thanks

[dustin.r...@gmail.com]

The tool should keep track of how many times the assertions is non-
vacuous passing which should indicate how often that is hit. You can
also use the 'cover' syntax to track coverage of a property, just like
an assertion except you use cover and you don't have error messages.

Otherwise if you want to use a coverpoint, you can instantiate
covergroups and coverpoints inside a module and use the .sample() of
the covergroup to sample on a bit that is set when a certain behavior
occurs.

[Essam Arshed]

Hi

I did you the the assertion method to get the coverage of that
property using the work "cover" but I read that the same tempral
property can be expressed using the covergroup and coverpoint and i
don't know how to do that from syntax point of view ???

Essam