Assertions for Duty Cycle

[kakar]

Hi All,

[kakar]

Hi

I have to write assertions in SV for duty cycle

My condition is that whener the signal "Master_select[3:0]"(changes
values on REF_CLK) has a value of 4'b0001 then the clock TX_PERM
should have a duty ratio of 40:60.


Master_select==3'b001 |-> (TX_PERM should have duty ratio of 40:60)
Master_select==3'b010 |-> (TX_PERM should have duty ratio of 50:50)
Master_select==3'b100 |-> (TX_PERM should have duty ratio of 60:40)...

Is it possible to write assertions for such kind of conditions ...
If we are able to generate a clock(gen_clk) such it has 5 times the
frequency of the TX_PERM.. then it night be possible...
But gen_clk should be synchronized to the TX_PERM...
Then we can have

@(posedge gen_clk)
($rose(TX_PERM) && Master_slect==3'b001) |-> ##2 $fell(TX_PERM) ##3
$rose(TX_PERM);

Since TX_PERM is controlled inside the design and has variable duty
ratio its not possible to generate gen_clk .

Any one has better ideas???



Regards
Tarun Kakar
AMD Markham, Canada

[Manmohan]

Hi,

One way of checking this is put some self checking verilog code ,for
example
collect the time stamp values of clock edges(both positive and
negative) in some
variables and based on your condition check for respective duty
cycles.
Hope its clear, there can be many other ways, others can put light.

Thanks
Manmohan