Coverage in SystemVerilog

[Essam]

Hi

I am trying to define coverage group and coverage point in SV but I
need some help. I have two Inputs or register A, B (reg [3:0] A & reg
[3:0] B), I want to cover the values when both A and B are equals. A
and B has 16 values each and cross product will produce 256 values.
But I need to detect only 16 cases when A=B like (0=0, 1=1,
2=2.....15=15)

So, I tried this

covergroup cvpt0 @(posedge clock);
coverpoint RA
{ bins a [] = {0}; }
coverpoint RB
{ bins b [] = {0};}
cvpt0cross: cross RA, RB;
endgroup

and I did creat 16 covergroup, is this right and am I missing
something or is there better way to do it ????


Essam

[hitesh mishra]

Hi Essam,

Althoug you are doing in the right way. But the other way of doing the same in just one covergroup  can be as follows.

covergroup cvpt0 @(posedge clock);
     coverpoint RA
               {

                   bins a0 = {0};
                   bins a1 = {1};
                   bins a2 = {2};
                    ...
                    ...
                    ...
                    bins a15 = {15};
             }
                  
     coverpoint RB
               {
                   bins b0 = {0};
                   bins b1 = {1};
                   bins b2 = {2};
                    ...
                    ...
                    ...
                    bins b15 = {15};
             }

      cvpt0cross: cross RA, RB
                {
                   bins AB0  = binsof (RA.a0) && binsof (RB.b0);
                   bins AB1  = binsof (RA.a1) && binsof (RB.b1);
                    ......
                    ......
                    ......
                    ......
                    bins AB15  = binsof (RA.a15) && binsof (RB.b15);

               }
            
 
endgroup

Hopefully it wil work.
--
Thanks & Regards

Hitesh  Mishra
Design Engineer
Freescale Semiconductor
Mobile: 09891272635
"Dont walk as if U rule the World, Walk as if U dont care who rules the World, Thats called ATTITUDE"

[Ray Salemi]

Why not just create a coverpoint for A==B?

On 5/29/08, Essam <essam...@gmail.com> wrote:
>

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[Essam]

ok, can you explain how ?
I am only interested when A=B and A and B are different reg or input

On May 29, 7:58 am, "Ray Salemi" <rdsal...@gmail.com> wrote:
> Why not just create a coverpoint for A==B?
>

> Help heal our country and change the world:http://my.barackobama.com/page/outreach/view/main/RaySalemi- Hide quoted text -
>
> - Show quoted text -

[Dave Rich]

I think you want

covergroup cvpt0 @(posedge clock);
coverpoint RA iff (RA==RB);
endgroup

[Ray Salemi]

You can also do

covergroup cvpt0 @(posedge clock);
    coverpoint A==B {
      ignore_bins diff = {0};
    }
endgroup

--

[hitesh mishra]

covergroup cvpt0 @(posedge clock);

    coverpoint A==B {
      ignore_bins diff = {0};
    }
endgroup

HI Essam is that working ?