Binding an interface instead of a module

[TheFatMan]

Hi,
I've been binding assertion modules to other modules quite
successfully. But recently, I've wanted
to bind an interface to a module and it's not elaborating. The 2
blocks are vhdl instantiated into the SV tb.

I've double checked the hierarchy and believe it is correct.

Here's an example of what I did. Any suggestions?

thanks
Greg

-------------
module harness;

intf_c intf_c_inst(); // interface
block_sv_module block_sv(.ports...); // SV tb wrapping vhdl entity
block_a and its sub-block b

bind block_sv.block_a.subblock_b intf_c
intf_c_inst(.x(internal_reg_ofsubblock_b)); // binding statement

...
//interface declaration
interface intf_c;
logic [3:0] x;
endinterface

...
//entity/architecture of b
entity subblock_b
...
architecture
signal internal_reg_ofsubblock_b std_logic_vector(3 downto 0);
...

[TheFatMan]

btw, the error i get :
"Number of positional association elements (1) exceeds number of
formals (0)."

[Ajeetha Kumari]

Hi Greg,

> btw, the error i get :
> "Number of positional association elements (1) exceeds number of
> formals (0)."
>

That gives the clue, looking at your interface definition:

interface intf_c;
logic [3:0] x;
endinterface

It has no "formals", but during bind you have:

> > bind block_sv.block_a.subblock_b intf_c
> > intf_c_inst(.x(internal_reg_ofsubblock_b)); // binding statement

^^^^^^^^

HTH
Ajeetha, CVC
www.noveldv.com

On Feb 5, 2008 9:36 PM, TheFatMan <bshem...@gmail.com> wrote:
>
> btw, the error i get :
> "Number of positional association elements (1) exceeds number of
> formals (0)."
>
>

--
Ajeetha Kumari
* A Pragmatic Approach to VMM Adoption
* SystemVerilog Assertions Handbook
* Using PSL/SUGAR
Design Verification Consultant,
Contemporary Verification Consultants Private Limited,
Bangalore, India, http://www.noveldv.com