Hi,
SVA allows sequence_match_item that allows any function/task call.
For instance:
property ahb_p;
@(posedge clk) hreq |=> [*1:5] hresp == OK, next_addr(cur_addr);
endproperty : ahb_p
Untested code both from syntax and from protocol perspective, but
should get you going with the directions.
Feel free to expand if needed.
BTW - we have a SVA class lined up for Feb 2nd as part of our week
long SystemVerilog class in Bangalore. Contact me offline if
interested in enrolling.
Ajeetha, CVC
www.noveldv.com
--
Ajeetha Kumari
* A Pragmatic Approach to VMM Adoption
* SystemVerilog Assertions Handbook
* Using PSL/SUGAR
Design Verification Consultant,
Contemporary Verification Consultants Private Limited,
Bangalore, India,
http://www.noveldv.com