Newbie question

[Dan Shupe]

Hi all,

I am new to this group, and to verification in general.

Can anyone recommend a good book (for a novice) for learning the
SystemVerilog language? I have never used Verilog (only VHDL), I have
never programmed in a high-level language (other than C), and I am not
familiar with things like "classes" and object-oriented programming
principles.

Thanks for any help or guidance that you can provide.

Dan

[Glasser, Mark]

Dan,

There are a whole bunch of books out there. Search for SystemVerilog or
verification on amazon.com One good place to start is "SystemVerilog for
Verification" by Chris Spear (published by Springer).

-- Mark

[Dan Shupe]

Mark,

I did that, but did not know which of those "whole bunch of books"
that came up would be the best for a beginner. Thanks for the
recommendation.

Dan

[Sean W. Smith]

I will add I think Writing Testbenches 3rd edition by Janick Bergeron is a
good intro book and the best overall book for people trying to learn modern
DV approaches. highly recommended reading...

Sean

-----Original Message-----
From: avm-...@googlegroups.com [mailto:avm-...@googlegroups.com] On
Behalf Of Dan Shupe
Sent: Thursday, June 19, 2008 2:20 PM
To: Advanced Verification Methodology User Group

[pv]

I just bought the brand new book "Step-by-Step Functional Verification
with SystemVerilog and OVM " by Sasan Iman (500 pages) and I can
recommend it highly. It is clearly written, has good examples, and has
comprehensive chapters on verification methodologies, SystemVerilog,
OVM, randomization, environment implementation and scenario
generation, assertion-based verification, and coverage modeling and
measurement.

- Peter

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[Dan Shupe]

Peter,

Does this book discuss how to go about writing a verification plan?

Dan

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[pv]

Yes, it has a 12-page (each page chapter on verification planning with
sub-chapters such as The Modern Verification Plan, Building the
Verification Plan, From Plan to Environment, Measuring Progress, and
Reacing to Results.

Janick's book has a 34-page chapter on verification planning.

I think, for a novice, it would be good to start with Janick's book,
wich is indeed very good, and then continue with Imans book which goes
more into detail with more advanced SystemVerilog features and also
has a comprehensive description of one of the (public domain) standard
SystemVerilog-based verification methodologies, OVM.

- Peter