Create a mini-VIP in SystemVerilog/VMM in 2 weeks

[cvc.tr...@gmail.com]

Hi,

Create a mini-VIP in SystemVerilog/VMM in 2 weeks
…a project driven incubation for Verification engineers

CVC (www.cvcblr.com) is announcing a 2-weeks intensive incubation on
SystemVerilog-VMM VIP creation challenge. This is primarily targeted
for recently displaced workers in ASIC domain looking to hone their
skills on SV/VMM with a project based experience. This incubation
starts with 2-day training, and then offers the attendees a real life
challenge of creating a mini-Verification IP for industry standard
designs such as DMA controller/I2S/I2C etc. Such incubation goes far
beyond a traditional training program to make the attendees experience
the power of modern verification techniques in a true real life
setting.

Duration
Topic
Duration
Verification Using SystemVerilog 2 days
Verification Methodology 2 days
Create min-VIP 6 days

As the incubation seats are limited we recommend you rush to register
ASAP.

Schedule:
Tentative: Start: September 16 at Bangalore

To attend this class, confirm your registration by sending an email to
training @ cvcblr.com
Ph: +91-9916176014, +91-80-42134156

Please include the following details in your email:
Name:
Company Name:
Contact Email ID:
Contact Number:

Regards
Jagadeesh