Passing tables in system verilog

[pankaj kamboj]

Hi,
      I have a table in the form of rows and fields as shown below

#  Reg       field_name       address              sw        hw            startbit    endbit   
   reg1.0                            0X000094          rw        rw            31           5                              
   reg1.0    fld1                  0X000094          ro        wo            4             0
   reg2.0                            0X0000A4          ro        wo            15          0                      
   reg1.1                           0X0000              rw        rw            31          9
   reg1.1    fld2                 0X0000              ro        wo            8           0                                
   reg2.1                          0X0000              ro        wo            15          0    


I want to parse or pass this table into my system verilog testbench. How can i do that?

Is there any system task in system verilog or i have to write my own parser.


Pankaj     

[Puneet]

Hello Pankaj,

There is no system task in system verilog for this. You need to write you own custom parser for that using the string functions.

~Puneet