Difference between sequence and property in SVA

[sundar]

Hi all,

I would like to know the difference between sequence and property in
SVA.
I belive that what ever we can do using sequence can be checked using
property.

The minimal differences I can see were
1. sequence cant be asserted
2.few operators like "not" cant be used in sequence
3.good practice to define clocks in properties and keep sequence
independent of clocks
4.while we can call a sequence within a clock definition from within
assert statement, calling a property with a clock definition from
within the asset statement is not allowed -> ie.,
a5c:assert property(@(posedge clk) propert_name); //not allowed

I would like to know more and actual purpose of sequence and property.

Thanks,
Sundar

[Dave Rich]

Sundar,

Formal terminology decomposes the general concept of an "assertion"
into four different layers: Boolean, Temporal, Modeling, and
Verification. They conceptually help you understand the different
behaviors surrounding assertions, and each layer builds on the
fundamentals of the previous layer. For example, the Boolean layer is
just a SystemVerilog Boolean expression. The Temporal layer defines
Boolean expression relationships over time. In SV, a sequence
represents the embodiment of the Temporal layer, however, a sequence
could represent a simple Boolean expression. The distinction between
sequences and properties makes it easier to define the operations and
semantics that go along with each construct.

There are many books on SVA out there. I recommend "Assertion-Based
Design 2nd Edition" by Harry foster, Adam Krolnick, and David Lacey.

Dave

[sundar]

Dave,

Thanks for your inputs.
I will refer the Assertion based design book suggested by you.

Regards,
Sundar