Frequency settings

[Børge Strand-Bergesen]

Hi guys, 

The UAC2 USB descriptors need a bit of an overhaul to work on the UAC2 driver in Microsoft's Win10 Creator's Update. The DAC works but is locked to 44.1. Supposedly, Windows will support all rates. At the time being I'm getting some help from the Wdmaudiodev list while searching for faulty clock and sample rate definitions, and possibly lacking reporting of those.

One of the things I find strainge in the code is the relationship between current_freq.frequency and current_freq.freq_bytes[] I guess the two have to be related for the Host to set the Devices's sample rate.

Do you know how one is converted to the other as the DAC is told to change sample rates, or requested to report it back to the Host? I struggle to see how .frequency is actually written.

The way I read the code, .freq_bytes are used for communication with EP_CONTROL while .frequency is used internally. I just can't find the link between them. 

Cheers,

Børge

[Alex Lee]

If current_freq is defined with a union then the two are related in the way (i.e. whether it is big endian or small endian) it is stored internally by the compiler and the endian of the endpoint transfer of bytes.

Alex

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[Børge Strand-Bergesen]

Thanks Alex, 

that explains things!

While we're at it, do you remember the reasoning behind

gpio_get_pin_value(AK5394_LRCK));

gpio_get_pin_value(AK5394_LRCK)); // exit when FS goes high

before 

pdca_enable(PDCA_CHANNEL_SSC_RX);

?

I've run into a similar problem where PDCA_CHANNEL_SSC_TX and the I2S interface some times cause an L/R swap. Each time I reset I get the same result, but if I change unrelated parts of the code I get a different L/R swap. I have yet to write fully systematic code which gives me the expected L/R swap. The bug is there somewhere in the way I2S and PDCA are set up. 

Børge

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