Hi Alex,
that would be nice! There are a few differences between DIb and module+AB-1. They are not very critical:
1) module+AB-1 will have a VBUS power enable pin to support suspend. It basically needs to be set to 1 in order to power the DAC and clocks. DIb doesn't have this pin.
2) DIb has a functional RS232 (works on your board, untested on mine). The module has IO for UART. I'll add an RS232 amp and connector on AB-1 but probably not populate the parts. The same may go for a display header. These two debug fuctions will probably not be power-gated by the VBUS power enable pin.
3) DIb receives its MCLK from the PLL in an off-board FPGA. So it has no clock selection. On your board I have patched in one 12.288MHz XO and one at 11.2896. The latter is connected to the MCLK net, and to switch to the former you'll have to bring out the soldering iron. Both XOs have an active-high enable pin with a week pull-up. These pins are not connected. It should be fairly easy to add 1k pull-downs and separate GPIO lines to turn them on one at a time. That way their outputs can be shorted to the MCLK net with small resistors. The module will support both this mechanism and a discrete Maxim MUX circuit.
But aside from testing the effects of XO swaps in SW, DIb should enable full debug of 44.1, 48, 88.2 and 96. We'll have to see how the DAC responds to 176.4 and 192, something it supposedly won't do on 11.2896 and 12.288MHz MCLK, respectively. But on AB-1 we will use twice the MCLK frequency and halve it before it enters the module.
At low volumes the NRE dominates over parts and labor. What I'm currently planning is to order maybe 10 module+AB-1 kits for early adopters, and hope that there are only major changes (not necessitating another full NRE) to make it work well. And then, with the protocols you outline working, I wish to go public with it. As it is now, the rarer parts (XOs and DACs) will not be mounted by the manufacturers, but after initial prototyping they will.
Cheers,
Børge