PAPER 11/27: Exploring Design space of future CMPs
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Guofeng
Nov 17, 2007, 12:55:37 PM11/17/07
to ASU:CSE520 FALL 07 Advanced Computer Architecture
Exploring the design space of future CMPs
Jaehyuk Huh Burger, D. Keckler, S.W.
Dept. of Comput. Sci., Texas Univ., Austin, TX ;
This paper appears in: Parallel Architectures and Compilation
Techniques, 2001. Proceedings. 2001 International Conference on
Publication Date: 2001
On page(s): 199-210
Meeting Date: 09/08/2001 - 09/12/2001
Location: Barcelona, Spain
ISBN: 0-7695-1363-8
References Cited: 26
INSPEC Accession Number: 7099070
Digital Object Identifier: 10.1109/PACT.2001.953300
Posted online: 2002-08-07 00:09:46.0
Jaehyuk Huh Burger, D. Keckler, S.W.
Dept. of Comput. Sci., Texas Univ., Austin, TX ;
This paper appears in: Parallel Architectures and Compilation
Techniques, 2001. Proceedings. 2001 International Conference on
Publication Date: 2001
On page(s): 199-210
Meeting Date: 09/08/2001 - 09/12/2001
Location: Barcelona, Spain
ISBN: 0-7695-1363-8
References Cited: 26
INSPEC Accession Number: 7099070
Digital Object Identifier: 10.1109/PACT.2001.953300
Posted online: 2002-08-07 00:09:46.0
David.S....@asu.edu
Nov 27, 2007, 3:56:05 PM11/27/07
to ASU:CSE520 FALL 07 Advanced Computer Architecture
Critique By David Phillips
This paper explores the future limitations that will be imposed on
Chip-Multi Processors (CMP)s. The author seeks to discover the most
optimzal organization that will maximize performance of future CMPs
per unit area.
The considerations made by the author include CPU type: in-order-
execution (smaller, simpler) or out-of-order execution (larger,
faster). The out-of-order super scalar CPU's are about 1.54x the size
of the in-order execution CPU. However, the out-of-order CPU
typically yields a performance gain of 54% which the author concludes
is sufficient to make the out-of-order CPU more efficient per unit of
area even though it takes up more space on the die than the in-order
CPU.
The author also considers cache sizes per core. The author finds that
as more cores are added to the die, the off-chip communication and
memory contention is going to impose fundamental limits on
performance. The author supplies data that shows that the number of
transistors on the die is going to increase at a much faster rate than
the number of signaling pins that are used for off-chip
communication. As a result, as the cores become smaller and more are
added to the die - the cache sizes for each core are going to have to
increase in order to prevent drastic increases in off-chip
communication.
The author considers 3 different classes of applications and
determines that different organizations work better for each class:
For processor bound applications (applications with little memory
access)
- Out-Of-Order Execution Cores
- 64 KB L2 caches since there are fewer memory accesses. Larger
cache not needed.
For cache sensitive applications (applications with moderate memory
accesses)
- Out-Of-Order Execution Cores
- 256 KB and larger caches
For bandwidth bound applications (applications with heavy memory
access)
- Out-of-Order Execution Cores (though difference to in-order cores
is negligible)
- 256 KB caches
Strengths of the paper
------------------------------------
Discovers that off-chip bandwidth is going to be a critical limiting
factor in future generations of CMPs which is going to force cache
sizes to increase. Increased cache size means that more area on the
chip will have to be devoted to the caches and leave less room for
additional cores. This will impose a fundamental limit to the number
of cores that can be effectively placed onto a single die.
The author also discovers that out-of-order execution cores and in-
order execution cores exhibit very similar performance behavior for
applications that are heavily bandwidth bound. However, the author
still believes that OOE cores are more suitable for bandwidth bound
applications because they make better use of the communication
channels.
Discovers that cache-sensitive applications will transition to CPU-
bound as the cache sizes increase and cache misses become much more
infrequent.
Weaknesses of the paper
---------------------------------------
Author assumes that all simulated operating processes are independent
of each other. Does not reflect a true server workload.
The simulations use latency speeds associated 70nm technology and do
not consider future improvements as the feature sizes become
smaller.
Simulations do not use true server workloads. They relies only on
SPEC2000 benchmarks.
Simulations do not consider power consumption which could impose more
stringent limits than off-chip bandwidth.
This paper explores the future limitations that will be imposed on
Chip-Multi Processors (CMP)s. The author seeks to discover the most
optimzal organization that will maximize performance of future CMPs
per unit area.
The considerations made by the author include CPU type: in-order-
execution (smaller, simpler) or out-of-order execution (larger,
faster). The out-of-order super scalar CPU's are about 1.54x the size
of the in-order execution CPU. However, the out-of-order CPU
typically yields a performance gain of 54% which the author concludes
is sufficient to make the out-of-order CPU more efficient per unit of
area even though it takes up more space on the die than the in-order
CPU.
The author also considers cache sizes per core. The author finds that
as more cores are added to the die, the off-chip communication and
memory contention is going to impose fundamental limits on
performance. The author supplies data that shows that the number of
transistors on the die is going to increase at a much faster rate than
the number of signaling pins that are used for off-chip
communication. As a result, as the cores become smaller and more are
added to the die - the cache sizes for each core are going to have to
increase in order to prevent drastic increases in off-chip
communication.
The author considers 3 different classes of applications and
determines that different organizations work better for each class:
For processor bound applications (applications with little memory
access)
- Out-Of-Order Execution Cores
- 64 KB L2 caches since there are fewer memory accesses. Larger
cache not needed.
For cache sensitive applications (applications with moderate memory
accesses)
- Out-Of-Order Execution Cores
- 256 KB and larger caches
For bandwidth bound applications (applications with heavy memory
access)
- Out-of-Order Execution Cores (though difference to in-order cores
is negligible)
- 256 KB caches
Strengths of the paper
------------------------------------
Discovers that off-chip bandwidth is going to be a critical limiting
factor in future generations of CMPs which is going to force cache
sizes to increase. Increased cache size means that more area on the
chip will have to be devoted to the caches and leave less room for
additional cores. This will impose a fundamental limit to the number
of cores that can be effectively placed onto a single die.
The author also discovers that out-of-order execution cores and in-
order execution cores exhibit very similar performance behavior for
applications that are heavily bandwidth bound. However, the author
still believes that OOE cores are more suitable for bandwidth bound
applications because they make better use of the communication
channels.
Discovers that cache-sensitive applications will transition to CPU-
bound as the cache sizes increase and cache misses become much more
infrequent.
Weaknesses of the paper
---------------------------------------
Author assumes that all simulated operating processes are independent
of each other. Does not reflect a true server workload.
The simulations use latency speeds associated 70nm technology and do
not consider future improvements as the feature sizes become
smaller.
Simulations do not use true server workloads. They relies only on
SPEC2000 benchmarks.
Simulations do not consider power consumption which could impose more
stringent limits than off-chip bandwidth.
jun shen
Nov 27, 2007, 10:13:24 PM11/27/07
to ASU:CSE520 FALL 07 Advanced Computer Architecture
critique by Jun Shen
Paper Outline
The paper explores how future CMP shall look like. The paper
mainly focuses on several important factors of the CMP design such as
processor organization, cache, off-chip bandwidth and application
characteristics. Of these factors, application characteristics receive
more attention. And at last the conclusion is that out-of-order core
is more area efficient. Due to the limit of bandwidth, L2 cache is
critical to throughput. Off-chip access will have a great impact on
the overall performance.
Contributions:
* The paper presents a systematic method of evaluating performance of
CMP.
* The paper gives the quantitative comparison between different design
option, for example between the out-of-order core and in-order core,
between different cache sizes.
* The paper validates different CMP options with all kinds of
benchmarks.
Weaknesses:
* The paper disregard certain factors which is vital to the CMP design
such as power consumption
* The benchmark SPEC2000 may not simulate the realistic server
workload.
* Due to wire delay, there is an upper limit of cache size which can
not be overcome.
Pradnyesh Gudadhe
Nov 28, 2007, 6:23:06 PM11/28/07
to asucse520-fall-07-advanc...@googlegroups.com
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