PAPER 11/08: Microarchitectural Techniques for power gating of functional units

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Guofeng

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Nov 5, 2007, 12:47:28 PM11/5/07
to ASU:CSE520 FALL 07 Advanced Computer Architecture
@inproceedings{1013249,
author = {Zhigang Hu and Alper Buyuktosunoglu and Viji Srinivasan and
Victor Zyuban and Hans Jacobson and Pradip Bose},
title = {Microarchitectural techniques for power gating of execution
units},
booktitle = {ISLPED '04: Proceedings of the 2004 international
symposium on Low power electronics and design},
year = {2004},
isbn = {1-58113-929-2},
pages = {32--37},
location = {Newport Beach, California, USA},
doi = {http://doi.acm.org/10.1145/1013235.1013249},
publisher = {ACM},
address = {New York, NY, USA},
}

Sugan Vinayagam

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Nov 12, 2007, 2:20:04 AM11/12/07
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Hi,

Please find my critique for the paper attached with this email.

Thanks,
Sugan.
Critique-1.pdf

Sugan Vinayagam

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Nov 12, 2007, 2:23:10 AM11/12/07
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Hi,

I forgot to include the references in the critique. Here it is:

References:
1. Digital Integrated Circuits - A Design Perspective - by Jan M.Rabaey, Anantha Chandrakasan, Borivoje Nikolic. Publisher - Perntice Hall - 2005 Edition.

Thanks,
Sugan.

Sugan Vinayagam




--
Sugan Vinayagam

YI-HSI...@asu.edu

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Nov 12, 2007, 7:26:18 PM11/12/07
to ASU:CSE520 FALL 07 Advanced Computer Architecture
Hi,

That's my critique for this paper.

Best regards,
Yi-hsin Tseng


Paper Title:Microarchitectural Techniques for power gating of
functional units
Critic:Yi-hsin Tseng

The main concern in current and future microprocessor designs is
Leakage power. In this paper, the authors presented a technique to
reduce leakage through power-gating of execution units. In the
introduction part, the authors point out the impact on power
dissipation which are subthreshold leakage and gate leakage
currents.

Two dynamic power-gating technique studied at program runtime is time-
based technique and branch prediction mechanism. In time-based
technique, they observe the state of an execution unit, and turn it
off after seeing a streak of idle cycles. On the other hand, in
branch prediction mechanism, if a branch is mispredicted, instructions
after the branch will be flushed from pipeline, and re-directed to the
current path. The conclusion is: Time based technique is efficient
for FP execution units which have high idle time; branch prediction
mechanism is efficient for integer execution units.

The strength in this paper is that architectural techniques can be
used effectively in power-gating units. They quantify the power
gating potential for different execution unit used a state-of-the-art
out-of-order superscalar processor model and SPEC2K suit. Their
experiments shows that a substantial leakage power reduction can be
reached in execution unit by power gating based on architectural
techniques. And for different techniques, they are efficient on
different units.

The weakness for this paper: first, in section2.2, they assume a
perfect predictor that can predict the idle intervals with no delay,
but a perfect predictor might not exist in the real world. Secondly,
as the presenter said, the paper doesn’t mention about the strength
and weakness of power gating over other circuit level approaches.
Thirdly, they applied a “sleep” signal to the gate of the header or
footer transistor to turn-off the supply voltage to the circuit block.
The authors didn’t mention about the additional power consumption
about it. Fourthly, in section 4, they assume there is no leakage
savings during wakeup, but they also point out that some leakage
savings could be achieved in the wakeup process, before the unit is
fully powered. This approach causes a contradiction in their
experiment. Fifthly, in section 2.1, they using equation (2) and (1)
and the leakage factor L by assuming that there is no leakage through
the header device. But I think it is impossible for this assumption,
the header device may have leakage opposed to their assumption.

Pradnyesh Gudadhe

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Nov 13, 2007, 5:21:44 AM11/13/07
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Please find critique attached with this email.
Thanks.

Regards,
Pradnyesh


Critique1.pdf

Mike

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Nov 16, 2007, 1:59:32 AM11/16/07
to ASU:CSE520 FALL 07 Advanced Computer Architecture
Summary of paper
This paper presents and analyzes the effectiveness of using
directional antenna on anchor nodes (nodes with a known location) for
localization of mobile nodes. Essentially signals are received with a
certain power value depending on their angle and distance from the
antenna. By solving a system of equations this angle and distance can
be estimated.
Three configurations were introduced by the author and a fourth case
was presented and analyzed as a baseline. Jay Elston made a very nice
summary of these cases.
1. Aligned Nodes
Anchor(s): Single anchor node using a single directional antenna,
Node
is aligned
Target: Two directional antenna, Target is aligned with anchor.
2. Omni-directional
Anchor(s): Single anchor node transmitting with Omni-directional
dipole antennas
Target: Two directional antenna, Target's alignment is known.
3. Unaligned Nodes
Anchor(s): Dual directional antennas, Anchor's alignment is known.
Target: Two directional antenna, Target is unaligned.
4. Dual anchor Nodes
Anchor(s): Two anchor nodes, each with Directional antenna, Anchor's
alignment is known.
Target: Single directional antenna, Target's alignment is known.

The experimental evaluation demonstrates that location estimation
using directional antennas is a significant improvement over omni-
directional approaches in cases where there are sufficient aligned
anchor nodes. The number of required anchor nodes increases if the
alignment of the target cannot be guaranteed and this should be a
consideration in designing a localization scheme for a specific
network. It was noted as a striking feature that this technique has
the ability to localize a target node with just one anchor node if the
beacon and target are aligned.

Main points in critiques and discussion
There is some concern that gain factor may be inaccurate for lower
values and that some probability math should be employed to account
for errors in readings.

It was noted that measuring power values at more than one receiving
antenna might be unrealistic because of shielding effects as the size
of the node increases. The critique wanted to see this factor
considered for more realistic error estimation.

Several critiques questioned some of the assumptions of the paper. For
instance the assumption of maximum possible directive gain (cos(BL/
2sin(angle)). Overall the critiques wanted the paper to discuss the
implications of when the assumptions made do not hold.

Discussion on the class blog mostly centered around which scheme would
be most appropriate for a generalized solution. The main perceived
problem was that the alignment of nodes can never be guaranteed at the
time of localization and so a variant of the unaligned case must be
used.

Conclusion
The overall conclusion of the critiques and discussion was that this
scheme is perfectly acceptable in cases where alignment can be
guaranteed and beacon density allows for some overlap. In cases where
this does not hold the use of directional antennas for localization is
not "highly justified" and network designers should consider
alternative schemes or will need to provide surplus beacon nodes to
overcome this shortcoming.

Thank you Shiraz Saleem, Aarti Munjal, and Jay Elston for your
insights and discussion.

Saleel Kudchadker

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Nov 16, 2007, 11:51:21 AM11/16/07
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Mike ,
 
 
I guess u messed up mobile computing summary with comp arch 2
 
Regards
 
Saleel
 

Raghu

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Nov 16, 2007, 12:21:26 PM11/16/07
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Hi!
 
The summary presented by you is not for this paper. This paper says about the power gating of execution units.
 
Regards
Sai Raghunath T

 
On 11/15/07, Mike <mjo...@asu.edu> wrote:
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