Sugan Vinayagam
That's my critique for this paper.
Best regards,
Yi-hsin Tseng
Paper Title:Microarchitectural Techniques for power gating of
functional units
Critic:Yi-hsin Tseng
The main concern in current and future microprocessor designs is
Leakage power. In this paper, the authors presented a technique to
reduce leakage through power-gating of execution units. In the
introduction part, the authors point out the impact on power
dissipation which are subthreshold leakage and gate leakage
currents.
Two dynamic power-gating technique studied at program runtime is time-
based technique and branch prediction mechanism. In time-based
technique, they observe the state of an execution unit, and turn it
off after seeing a streak of idle cycles. On the other hand, in
branch prediction mechanism, if a branch is mispredicted, instructions
after the branch will be flushed from pipeline, and re-directed to the
current path. The conclusion is: Time based technique is efficient
for FP execution units which have high idle time; branch prediction
mechanism is efficient for integer execution units.
The strength in this paper is that architectural techniques can be
used effectively in power-gating units. They quantify the power
gating potential for different execution unit used a state-of-the-art
out-of-order superscalar processor model and SPEC2K suit. Their
experiments shows that a substantial leakage power reduction can be
reached in execution unit by power gating based on architectural
techniques. And for different techniques, they are efficient on
different units.
The weakness for this paper: first, in section2.2, they assume a
perfect predictor that can predict the idle intervals with no delay,
but a perfect predictor might not exist in the real world. Secondly,
as the presenter said, the paper doesn’t mention about the strength
and weakness of power gating over other circuit level approaches.
Thirdly, they applied a “sleep” signal to the gate of the header or
footer transistor to turn-off the supply voltage to the circuit block.
The authors didn’t mention about the additional power consumption
about it. Fourthly, in section 4, they assume there is no leakage
savings during wakeup, but they also point out that some leakage
savings could be achieved in the wakeup process, before the unit is
fully powered. This approach causes a contradiction in their
experiment. Fifthly, in section 2.1, they using equation (2) and (1)
and the leakage factor L by assuming that there is no leakage through
the header device. But I think it is impossible for this assumption,
the header device may have leakage opposed to their assumption.