Hi, Ayan,
In paper" Bypass Aware Instruction Scheduling for Register File Power
Reduction"
the power reduction in this paper is achieved by scheduling instructions so
that they transfer operand values via bypasses, instead of reading them from
the register file.
By doing this, compiler needs to know something like
When does an instruction bypass result?
Which operands can read the result?
When result is written into register file?
This information is related to the hardware architecture. For example, what
kind
of pipeline is used, what the stage of this pipeline,etc.
This paper just implemented some scheduling algorithms on a specific
hardware platform, i.e. Intel XScale processor. Compilers need to support
different architectures and doing optimization on different platforms to
ensure that the proposed scheduling algorithms are generic and can be used
widely. At this point, the develop cost for compiler and software support
may be very high
Hope this answered your question
Regards,
Tao