PAPER 11/13: Generating FPGA-Accelerated DFT Libraries

[Guofeng]

Generating FPGA-Accelerated DFT Libraries

D'Alberto, Paolo Milder, Peter A. Sandryhaila, Aliaksei
Franchetti, Franz Hoe, James C. Moura, Jose M.F. Puschel,
Markus Johnson, Jeremy R.
Yahoo!;

This paper appears in: Field-Programmable Custom Computing Machines,
2007. FCCM 2007. 15th Annual IEEE Symposium on
Publication Date: 23-25 April 2007
On page(s): 173-184
ISBN: 978-0-7695-2940-0
Digital Object Identifier: 10.1109/FCCM.2007.34
Posted online: 2007-09-04 09:29:18.0

[Raghu]

Hi,

 

Please fnd my critic on the paper, "Generating FPGA-Accelerated DFT Libraries" attached.

 

Thanks & Regards

Sai Raghunath T

 

[Rob Duckles]

Critique:

* Strengths:
Supported by abundant benchmarks; details the performance of various
combinations of hardware/software for 1D and 2D Fourier transforms.
Able to minimize power and maximize performance by combining
programmable hardware (FPGA) with software.
A lot of statistics to benefit implementors; for example, given the
constraints of an application, an optimal combination of hardware/
software could be found.

*Weaknesses
Presented equations instead of going into an overview of what a
Fourier transform really does; if I hadn't known before-hand, I
wouldn't have understood much of the presentation.
Some of the results were presented without explaining why they
occurred; for example, the presentation did not explain why the SNR
got smaller as the problem size got bigger.

On Nov 14, 10:42 am, Raghu <sairaghun...@gmail.com> wrote:
> Hi,
>
> Please fnd my critic on the paper, "Generating FPGA-Accelerated DFT
> Libraries" attached.
>
> Thanks & Regards
> Sai Raghunath T
>

> On 11/13/07, Guofeng <guofeng.d...@gmail.com> wrote:
>
>
>
> > Generating FPGA-Accelerated DFT Libraries
>
> > D'Alberto, Paolo Milder, Peter A. Sandryhaila, Aliaksei
> > Franchetti, Franz Hoe, James C. Moura, Jose M.F. Puschel,
> > Markus Johnson, Jeremy R.
> > Yahoo!;
>
> > This paper appears in: Field-Programmable Custom Computing Machines,
> > 2007. FCCM 2007. 15th Annual IEEE Symposium on
> > Publication Date: 23-25 April 2007
> > On page(s): 173-184
> > ISBN: 978-0-7695-2940-0
> > Digital Object Identifier: 10.1109/FCCM.2007.34
> > Posted online: 2007-09-04 09:29:18.0
>
>
>

> critic for FPGA accelearted DFT libraries.doc
> 33KDownload

[Raghu]

Hi

 

I forgot to add reference to my critc.

 

B.P. Lathi,"Signal processing and Linear systems" Oxford University Press, June 1998

 

Thanks & Regards

Sai Raghunath T

 

--
Regards
Sai Raghunath T

[ash...@gmail.com]

Hi

Here's my critique for the paper:

The paper describes a significant extension to software-only
frameworks such as Spiral, to support optimal hardware-software
partitioning. This extension operates by finding the most optimal
hardware design size for a given problem and then synthesizing it
using a combination of hardware and software given available hardware
kernel sizes.

Strengths:
- The framework (Spiral) considers various factors such as execution
time, power, error and accordingly optimise the design
- Application of heuristics (timing behavior) and optimizations
(ignoring inefficient DFT sizes, use of dynamic programming) to reduce
the search space and hence, the time spent in selecting the most
optimal hardware design.
- Ability to compute DFTs of sizes that are not powers of two.
- Even when the problem size is greater than the size of the core,
the performance of the system is still double that of a software-only
solution (considering that majority of the computation in such cases
is handled in software).

Weakness:
- Based on heuristic information, the system generates certain
number of hardware designs that are likely to give high performance.
Considerable time spent in getting performance data for a single
hardware design (approx. 30 mins). Hence the process is slow.
- A significant amount of time is spent in communication between
FPGA and the processor


Ashay

On Nov 15, 9:33 am, Raghu <sairaghun...@gmail.com> wrote:
> Hi
>
> I forgot to add reference to my critc.
>
> B.P. Lathi,"Signal processing and Linear systems" Oxford University Press,
> June 1998
>
> Thanks & Regards
> Sai Raghunath T
>

> On 11/14/07, Raghu <sairaghun...@gmail.com> wrote:
>
>
>
>
>
> > Hi,
>
> > Please fnd my critic on the paper, "Generating FPGA-Accelerated DFT
> > Libraries" attached.
>
> > Thanks & Regards
> > Sai Raghunath T
>

[Sushma Myneni]

Hi,

Please check the attached for the summary on this paper.

Thankyou,
Sushma

> B.P . Lathi,"Signal processing and Linear systems" Oxford University Press,