PAPER 11/27: Limits of Instruction-Level Parallelism
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Guofeng
Nov 17, 2007, 12:54:46 PM11/17/07
to ASU:CSE520 FALL 07 Advanced Computer Architecture
@inproceedings{106991,
author = {David W. Wall},
title = {Limits of instruction-level parallelism},
booktitle = {ASPLOS-IV: Proceedings of the fourth international
conference on Architectural support for programming languages and
operating systems},
year = {1991},
isbn = {0-89791-380-9},
pages = {176--188},
location = {Santa Clara, California, United States},
doi = {http://doi.acm.org/10.1145/106972.106991},
publisher = {ACM},
address = {New York, NY, USA},
}
author = {David W. Wall},
title = {Limits of instruction-level parallelism},
booktitle = {ASPLOS-IV: Proceedings of the fourth international
conference on Architectural support for programming languages and
operating systems},
year = {1991},
isbn = {0-89791-380-9},
pages = {176--188},
location = {Santa Clara, California, United States},
doi = {http://doi.acm.org/10.1145/106972.106991},
publisher = {ACM},
address = {New York, NY, USA},
}
peyman...@gmail.com
Nov 29, 2007, 1:49:39 PM11/29/07
to ASU:CSE520 FALL 07 Advanced Computer Architecture
Paper review:
This old research report, brought into light the different limitations
that exist in improving the performance of applications by instruction
level parallelism. It explains techniques such as register renaming,
alias analysis, branch prediction, etc and then shows how each of
these techniques are limited in the amount of improvements they can
provide.
Strengths:
-Detailed description of the common techniques used to increase ILP
-Statistics showing the effect each of these techniques has on
increasing the level of parallelism
-The limits of each of the techniques from a practical as well as
mathematical point of view
Weaknesses:
-Although each of the techniques are well studied individually, little
effort is made in showing how all of them will perform when deployed
together or if using a combination of them may have side effects in
the level of parallelism. I can't see the seven models they propose
(page 19) as a valid study in the effect these techniques have on each
other, since they are predefining the efficiency of them when used
together without a scientific basis.
-The models they describe are incredibly optimistic however that is
perhaps a necessity when writing futuristic papers.
This old research report, brought into light the different limitations
that exist in improving the performance of applications by instruction
level parallelism. It explains techniques such as register renaming,
alias analysis, branch prediction, etc and then shows how each of
these techniques are limited in the amount of improvements they can
provide.
Strengths:
-Detailed description of the common techniques used to increase ILP
-Statistics showing the effect each of these techniques has on
increasing the level of parallelism
-The limits of each of the techniques from a practical as well as
mathematical point of view
Weaknesses:
-Although each of the techniques are well studied individually, little
effort is made in showing how all of them will perform when deployed
together or if using a combination of them may have side effects in
the level of parallelism. I can't see the seven models they propose
(page 19) as a valid study in the effect these techniques have on each
other, since they are predefining the efficiency of them when used
together without a scientific basis.
-The models they describe are incredibly optimistic however that is
perhaps a necessity when writing futuristic papers.
Aarul Jain
Nov 29, 2007, 2:04:25 PM11/29/07
to asucse520-fall-07-advanc...@googlegroups.com
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