PAPER 11/08: HyperTransport Technology
Guofeng
Rob Duckles
* Summary:
Aging bus architectures (such as PCI) are inadequate for some modern
day applications such as gigabit ethernet and 3d graphics. Overall,
the performance of processors have increased much faster than the
bandwidth and latency of buses, leaving the bus as a bottleneck.
HyperTransport was created to solve these problems, providing
dramatically superior bandwidth and latency.
* Strengths:
The paper conveyed the uniqueness in the overall implementation of
HyperTransport. In particular, HyperTransport is unique for using 2
pins-per-bit and representing data by the disparity of voltages
between two wires. The lower latency is attributed to the smaller
voltage changes needed.
The paper successfully contrasts HyperTransport to it's more-modern
competitor: PCI-Express. Indeed, HyperTransport in many ways beats
its younger brother.
The paper explains disadvantages, such as a higher pin count.
* Weaknesses:
There is a lack of concrete benchmarks. Specific 3-way comparisons
between PCI, PCI-Express, and HyperTransport could be very useful; in
particular, benchmark information could allow implementors to make
better design decisions (e.g., to use HyperTransport for lower voltage
and higher bandwidth, or PCI-Express for lower pin count).
More competitors could be described. Is ISA still relevant in any
circumstances? Are there any future bus architectures that might
replace HyperTransport?
On Nov 8, 3:15 pm, Guofeng <guofeng.d...@gmail.com> wrote:
> http://www.hypertransport.org/
peyman...@gmail.com
Transport Technology as the current best high speed IO link. The
technology is introduced as a major breakthrough for the communication
speed of in-the-box IO links, which was lagging in performance in the
last years.
Details of the architecture are properly explained in the paper and
the different layers are well defined. The only obscure claim of the
paper is that they utilize minimal number of pins in their
architecture (Page 9), which means less power consumption, thermal
problems and economic cost. However they fail to provide any proof as
to why their design will result in the minimum number of pins, they
simply compare it to other available technologies.
Mike
The comparisons shown in the slide were created by the presenter. The
paper does some minor comparison to PCI-X in so far as the claim
Hypertransport is 49 times faster.
Additionally, Hypertransport uses 4 pins per bit for 2 way data
channels, 2 pins per bit per direction. You may wish to clarify this.
>
> - Show quoted text -
Tao (Tony) Liu
Rgs,
Tao Liu
On Nov 8, 2007 3:15 PM, Guofeng <guofen...@gmail.com> wrote:
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> http://www.hypertransport.org/
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