Clarification on Timeline Visualizer

[Mohammad Khoddam]

Dear Astrasim Team, 

I hope this message finds you well. I work on a project with a dependency on Astrasim. I tried to generate a proper timeline visualizer to illustrate the program behaviors using the common VGG, Resnet workloads. In each simulation with different configurations, I always end up with continuous timeline bars without any exposed communication time. (Here is the respective GitHub issue: https://github.com/astra-sim/astra-sim/issues/267). I saw the video on your latest conference, and it seems like you are capable of generating proper timelines like the image below. Can you please help me with this problem?

Best,

Mohammad