Error in the diagram Figure B.4 Appendix B - Hardware Basics

[Munesh Singh]

I have two versions of the book and find the Figure B.4 on page 473 bit confusing. It mentions about cacheless NUMA but the diagram show NUMA with cache (ccNUMA). Can anyone please clarify on this?

[Yigal Hoffner]

Hello  Munesh 

If my understanding is correct - the parallelogram shapes next to each processor in the mesh represent the local memory of each processor (and not a cache). There are no caches which cache data from other processors - and hence - every time a processor wants to access the memory of another processor - it has to go all the way there. 

If there were caches - the first access would have brought the data to that cache. But this is not the case and therefore the overhead of single, but more so of continuous access to a remote memory is considerable compared to local access. 

In any case - imagine trying to have a cache coherence protocol in such a configuration! Never mind how difficult it can be - i doubt if it can be made reasonably efficient. 

Regards,

yigal

----------------------------------------------------------

Yigal Hoffner, PhD.
Senior Lecturer
Department of Software Engineering
Shenkar College of Engineering and Design
Israel
Email: yigal....@gmail.com

Work:   +972 3 611 0072

Mobile: +972 54 2196 177

On 16 February 2018 at 14:17, 'Munesh Singh' via Art of Multiprocessor Programming <art-of-multiprocessor-progr...@googlegroups.com> wrote:

I have two versions of the book and find the Figure B.4 on page 473 bit confusing. It mentions about cacheless NUMA but the diagram show NUMA with cache (ccNUMA). Can anyone please clarify on this?

---

The information contained in this message and any file and/or attachment transmitted herewith is confidential and may be legally privileged. It is intended solely for the use of the addressee and must not be disclosed to or used by anyone other than the addressee. If you receive this transmission by error, please notify the sender immediately by reply e-mail and destroy the original transmission and its attachments. If you are not the intended recipient, please be advised that viewing, copying, forwarding, printing and disseminating any information related to this mail is prohibited and you should not take any action based on the content of this mail and/or the attachments

--
You received this message because you are subscribed to the Google Groups "Art of Multiprocessor Programming" group.
To unsubscribe from this group and stop receiving emails from it, send an email to art-of-multiprocessor-programming+unsubscribe@googlegroups.com.
To post to this group, send email to art-of-multiprocessor-programmi...@googlegroups.com.
Visit this group at https://groups.google.com/group/art-of-multiprocessor-programming.
For more options, visit https://groups.google.com/d/optout.

[Munesh Singh]

Hi Yigal,

Many thanks for clarifying the issue over caches. I agree that the parallelogram shapes next to the mesh structure are local main memories and not caches. These combined form the global memory. So I think that first a data is looked (accessed) locally and then over the mesh. And this results in increased mesh traffic due to the broadcast.

If you observe carefully at the diagram, the left figure represents NUMA whereas the right one represents SMP, which erroneously is wrongly mentioned in the diagram title.

Thanks.

Regards

Dr. Munesh Singh Chauhan

Head of Major (Software)

College of Applied Sciences, Ibri

Ministry of Higher Education, Sultanate of Oman

munes...@cas.edu.om

Ext: 433

www.ibri.cas.edu.om

To post to this group, send email to art-of-multiprocessor-progr...@googlegroups.com.