Thumb2 ISS and Assembler questions.

[tartaru...@gmail.com]

Hello,

I am a undergraduate student and try to build a Thumb2 ISS.

While Thumb2 processors need to fetch 32 bits but handle 16- or 32-bit instructions, I'd like to know if the ArchC decoder detects whether the 32-bit fetch has 2 16-bit instructions or a 16-bit instruction and part of a 32-bit command included. Or is there a way to edit the PC content before decoding?

I would also like to create an assembler. The documentation says that a operand field that is declared in a format, must be defined for each operand identifier. However, the opcode of Thumb2, unlike that of ARM, does not include any conditional fields. These are stored separately in the APSR. So is there any way for the assembler to distinguish between expressions like "addeq" and "addne" even though they have the same opcode?

Thanks and greetings. :)

[Rafael Auler]

The decoder should work with variable-length instructions. So it
should detect whether you are working with a single 16-bit instruction
or a 32-bit one. However, if you need to know whether your PC is
aligned at 4 bytes in order to use a different decoding map, then I
think this case wouldn't be covered.

The assembler is tied to the encoded opcode. The PSRs are part of the
current program state, not part of the instruction stream. Maybe I'm
missing something but if the official arm assembler does recognize
"addeq", then this is probably a pseudo instruction that emits two
instructions, one to update the PSR and another to do a "addcc"
(conditionally add based on the PSR state). The assembler created by
ArchC supports pseudo instructions, you just specify the list of real
instructions corresponding to one pseudo instruction.

Best,
Rafael

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